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IEEE Micro
November/December 2003 (vol. 23 no. 6)
ISSN: 0272-1732
Table of Contents
Columns and Departments
Letters
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pp. 5
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Where we're going
(Abstract)
Richard Mateosian
pp. 6-7
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Features
Guest Editors' Introduction: Micro's Top Picks from Microarchitecture Conferences
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Charles Moore
, The University of Texas at Austin
Kevin W. Rudd
, Intel
Ruby B. Lee
, Princeton University
Pradip Bose
, IBM T.J. Watson Research
pp. 8-10
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Checkpoint Processing and Recovery: An Efficient, Scalable Alternative to Reorder Buffers
(Abstract)
Haitham Akkary
, Portland State University
Ravi Rajwar
, Intel Microarchitecture Research Lab
Srikanth T. Srinivasan
, Intel Microarchitecture Research Lab
pp. 11-19
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Runahead Execution: An Effective Alternative to Large Instruction Windows
(Abstract)
Onur Mutlu
, The University of Texas at Austin
Jared Stark
, Intel Microarchitecture Research Lab
Chris Wilkerson
, Intel Microarchitecture Research Lab
Yale N. Patt
, The University of Texas at Austin
pp. 20-25
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The Jrpm System for Dynamically Parallelizing Sequential Java Programs
(Abstract)
Michael K. Chen
, Stanford University
Kunle Olukotun
, Stanford University
pp. 26-35
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Scalable Vector Processors for Embedded Systems
(Abstract)
Christoforos E. Kozyrakis
, Stanford University
David A. Patterson
, University of California at Berkeley
pp. 36-45
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Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture
(Abstract)
Karthikeyan Sankaralingam
, The University of Texas at Austin
Ramadass Nagarajan
, The University of Texas at Austin
Haiming Liu
, The University of Texas at Austin
Changkyu Kim
, The University of Texas at Austin
Jaehyuk Huh
, The University of Texas at Austin
Doug Burger
, The University of Texas at Austin
Stephen W. Keckler
, The University of Texas at Austin
Charles Moore
, The University of Texas at Austin
pp. 46-51
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Temperature-Aware Computer Systems: Opportunities and Challenges
(Abstract)
Kevin Skadron
, University of Virginia
Mircea R. Stan
, University of Virginia
Wei Huang
, University of Virginia
Sivakumar Velusamy
, University of Virginia
Karthik Sankaranarayanan
, University of Virginia
David Tarjan
, University of Virginia
pp. 52-61
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Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor
(Abstract)
Grigorios Magklis
, Intel
Greg Semeraro
, Rochester Institute of Technology
David H. Albonesi
, University of Rochester
Steven G. Dropsho
, University of Rochester
Sandhya Dwarkadas
, University of Rochester
Michael L. Scott
, University of Rochester
pp. 62-68
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Measuring Architectural Vulnerability Factors
(Abstract)
Shubhendu S. Mukherjee
, Intel
Christopher T. Weaver
, Intel, University of Michigan
Joel Emer
, Intel
Steven K. Reinhardt
, Intel, University of Michigan
Todd Austin
, University of Michigan
pp. 70-75
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Transient-Fault Recovery for Chip Multiprocessors
(Abstract)
Mohamed A. Gomaa
, Purdue University
Chad Scarbrough
, Purdue University
T. N. Vijaykumar
, Purdue University
Irith Pomeranz
, Purdue University
pp. 76-83
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Discovering and Exploiting Program Phases
(Abstract)
Timothy Sherwood
, University of California at Santa Barbara
Erez Perelman
, University of California at San Diego
Greg Hamerly
, University of California at San Diego
Suleyman Sair
, North Carolina State University
Brad Calder
, University of California at San Diego
pp. 84-93
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Addressing Workload Variability in Architectural Simulations
(Abstract)
Alaa R. Alameldeen
, University of Wisconsin-Madison
David A. Wood
, University of Wisconsin-Madison
pp. 94-98
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Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches
(Abstract)
Changkyu Kim
, The University of Texas at Austin
Doug Burger
, The University of Texas at Austin
Stephen W. Keckler
, The University of Texas at Austin
pp. 99-107
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Token Coherence: A New Framework for Shared-Memory Multiprocessors
(Abstract)
Milo M.K. Martin
, University of Wisconsin-Madison
Mark D. Hill
, University of Wisconsin-Madison
David A. Wood
, University of Wisconsin-Madison
pp. 108-116
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Transactional Execution: Toward Reliable, High-Performance Multithreading
(Abstract)
Ravi Rajwar
, Intel Microarchitecture Research Lab
James Goodman
, University of Auckland
pp. 117-125
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Speculative Synchronization: Programmability and Performance for Parallel Codes
(Abstract)
Jos? F. Mart?nez
, Cornell University
Josep Torrellas
, University of Illinois at Urbana-Champaign
pp. 126-134
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Annual Index
2003 IEEE Micro Annual Index, Vol. 23
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pp. 136-144
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