Transient-Fault Recovery for Chip Multiprocessors

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	Similar Articles Articles by Mohamed A. Gomaa Articles by Chad Scarbrough Articles by T. N. Vijaykumar Articles by Irith Pomeranz

November/December 2003 (vol. 23 no. 6)

pp. 76-83

	ASCII Text	x
	Mohamed A. Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith Pomeranz, "Transient-Fault Recovery for Chip Multiprocessors," IEEE Micro, vol. 23, no. 6, pp. 76-83, November/December, 2003.

	BibTex	x
	@article{ 10.1109/MM.2003.1261390, author = {Mohamed A. Gomaa and Chad Scarbrough and T. N. Vijaykumar and Irith Pomeranz}, title = {Transient-Fault Recovery for Chip Multiprocessors}, journal ={IEEE Micro}, volume = {23}, number = {6}, issn = {0272-1732}, year = {2003}, pages = {76-83}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2003.1261390}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Micro TI - Transient-Fault Recovery for Chip Multiprocessors IS - 6 SN - 0272-1732 SP76 EP83 EPD - 76-83 A1 - Mohamed A. Gomaa, A1 - Chad Scarbrough, A1 - T. N. Vijaykumar, A1 - Irith Pomeranz, PY - 2003 VL - 23 JA - IEEE Micro ER -

Mohamed A. Gomaa, Purdue University

Chad Scarbrough, Purdue University

T. N. Vijaykumar, Purdue University

Irith Pomeranz, Purdue University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2003.1261390

Chip-level redundant threading with recovery (CRTR) for chip multiprocessors extends previous transient-fault detection schemes to provide fault recovery. To hide interprocessor latency, CRTR uses a long slack enabled by asymmetric commit and uses the trailing thread state for recovery. CRTR increases bandwidth supply by pipelining communication paths and reduces bandwidth demand by extending the dependence-based checking elision.

Citation:

Mohamed A. Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith Pomeranz, "Transient-Fault Recovery for Chip Multiprocessors," IEEE Micro, vol. 23, no. 6, pp. 76-83, Nov./Dec. 2003, doi:10.1109/MM.2003.1261390

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