Runahead Execution: An Effective Alternative to Large Instruction Windows

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November/December 2003 (vol. 23 no. 6)

pp. 20-25

	ASCII Text	x
	Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt, "Runahead Execution: An Effective Alternative to Large Instruction Windows," IEEE Micro, vol. 23, no. 6, pp. 20-25, November/December, 2003.

	BibTex	x
	@article{ 10.1109/MM.2003.1261383, author = {Onur Mutlu and Jared Stark and Chris Wilkerson and Yale N. Patt}, title = {Runahead Execution: An Effective Alternative to Large Instruction Windows}, journal ={IEEE Micro}, volume = {23}, number = {6}, issn = {0272-1732}, year = {2003}, pages = {20-25}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2003.1261383}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Micro TI - Runahead Execution: An Effective Alternative to Large Instruction Windows IS - 6 SN - 0272-1732 SP20 EP25 EPD - 20-25 A1 - Onur Mutlu, A1 - Jared Stark, A1 - Chris Wilkerson, A1 - Yale N. Patt, PY - 2003 VL - 23 JA - IEEE Micro ER -

Onur Mutlu, The University of Texas at Austin

Jared Stark, Intel Microarchitecture Research Lab

Chris Wilkerson, Intel Microarchitecture Research Lab

Yale N. Patt, The University of Texas at Austin

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2003.1261383

An instruction window that can tolerate latencies to DRAM memory is prohibitively complex and power hungry. To avoid having to build such large windows, runahead execution uses otherwise-idle clock cycles to achieve an average 22 percent performance improvement for processors with instruction windows of contemporary sizes. This technique incurs only a small hardware cost and does not significantly increase the processor's complexity.

Citation:

Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt, "Runahead Execution: An Effective Alternative to Large Instruction Windows," IEEE Micro, vol. 23, no. 6, pp. 20-25, Nov./Dec. 2003, doi:10.1109/MM.2003.1261383

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