Power Consumption Modeling and Characterization of the TI C6201 September/October 2003 (vol. 23 no. 5) pp. 40-49
This new approach characterizes power dissipation on complex DSPs. Its processor model relies on an initial functional-level power analysis of the target processor together with a characterization that qualifies the more significant architectural and algorithmic parameters for power dissipation. These parameters come from a simple profiling of the assembly code. This functional model accounts for deeply pipelined, superscalar, and hierarchical memory architectures.
Citation:
Nathalie Julien, Johann Laurent, Eric Senn, Eric Martin, "Power Consumption Modeling and Characterization of the TI C6201," IEEE Micro, vol. 23, no. 5, pp. 40-49, Sep./Oct. 2003, doi:10.1109/MM.2003.1240211 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||