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The iCore 520-MHz Synthesizable CPU Core
May/June 2003 (vol. 23 no. 3)
pp. 46-57
ASCII Text
x 
 
Nick Richardson, Lun Bin Huang, Razak Hossain, Julian Lewis, Tommy Zounes, Naresh Soni, "The iCore 520-MHz Synthesizable CPU Core," IEEE Micro, vol. 23, no. 3, pp. 46-57, May/June, 2003.
 
 
BibTex
x
 
@article{ 10.1109/MM.2003.1209466,
author = {Nick Richardson and Lun Bin Huang and Razak Hossain and Julian Lewis and Tommy Zounes and Naresh Soni},
title = {The iCore 520-MHz Synthesizable CPU Core},
journal ={IEEE Micro},
volume = {23},
number = {3},
issn = {0272-1732},
year = {2003},
pages = {46-57},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2003.1209466},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - The iCore 520-MHz Synthesizable CPU Core
IS - 3
SN - 0272-1732
SP46
EP57
EPD - 46-57
A1 - Nick Richardson,
A1 - Lun Bin Huang,
A1 - Razak Hossain,
A1 - Julian Lewis,
A1 - Tommy Zounes,
A1 - Naresh Soni,
PY - 2003
VL - 23
JA - IEEE Micro
ER -
 
Nick Richardson, STMicroelectronics
Lun Bin Huang, STMicroelectronics
Razak Hossain, STMicroelectronics
Julian Lewis, STMicroelectronics
Tommy Zounes, STMicroelectronics
Naresh Soni, STMicroelectronics

A new implementation of the ST20-C2 CPU architecture involves an eight-stage pipeline with hardware support to execute up to three instructions per cycle. The design operates up to 520 MHz at 1.8V, among the highest reported speeds for a synthesized CPU core.

Citation:
Nick Richardson, Lun Bin Huang, Razak Hossain, Julian Lewis, Tommy Zounes, Naresh Soni, "The iCore 520-MHz Synthesizable CPU Core," IEEE Micro, vol. 23, no. 3, pp. 46-57, May/June 2003, doi:10.1109/MM.2003.1209466
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