Efficient Construction of Aliasing-Free Compaction Circuitry
September/October 2002 (vol. 22 no. 5)
pp. 82-92
ASCII Text
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Ozgur Sinanoglu, Alex Orailoglu,
"Efficient Construction of Aliasing-Free Compaction Circuitry,"
IEEE Micro, vol. 22, no. 5, pp. 82-92, September/October, 2002.
BibTex
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@article{
10.1109/MM.2002.1044302, author = {Ozgur Sinanoglu and Alex Orailoglu}, title = {Efficient Construction of Aliasing-Free Compaction Circuitry}, journal ={IEEE Micro}, volume = {22}, number = {5}, issn = {0272-1732}, year = {2002}, pages = {82-92}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2002.1044302}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
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TY - MGZN JO - IEEE Micro TI - Efficient Construction of Aliasing-Free Compaction Circuitry IS - 5 SN - 0272-1732 SP82 EP92 EPD - 82-92 A1 - Ozgur Sinanoglu, A1 - Alex Orailoglu, PY - 2002 VL - 22 JA - IEEE Micro ER -
Parallel testing of cores can reduce soc test times, but the finite number of chip I/Os limits such parallelism. Space and time compaction can maximize parallelism by minimizing the required test bandwidth at the core outputs.
Citation:
Ozgur Sinanoglu, Alex Orailoglu, "Efficient Construction of Aliasing-Free Compaction Circuitry," IEEE Micro, vol. 22, no. 5, pp. 82-92, Sep./Oct. 2002, doi:10.1109/MM.2002.1044302
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