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A Hierarchical Test Methodology for Systems on Chip
September/October 2002 (vol. 22 no. 5)
pp. 69-81
ASCII Text
x 
 
Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin, "A Hierarchical Test Methodology for Systems on Chip," IEEE Micro, vol. 22, no. 5, pp. 69-81, September/October, 2002.
 
 
BibTex
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@article{ 10.1109/MM.2002.1044301,
author = {Jin-Fu Li and Hsin-Jung Huang and Jeng-Bin Chen and Chih-Pin Su and Cheng-Wen Wu and Chuang Cheng and Shao-I Chen and Chi-Yi Hwang and Hsiao-Ping Lin},
title = {A Hierarchical Test Methodology for Systems on Chip},
journal ={IEEE Micro},
volume = {22},
number = {5},
issn = {0272-1732},
year = {2002},
pages = {69-81},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2002.1044301},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - A Hierarchical Test Methodology for Systems on Chip
IS - 5
SN - 0272-1732
SP69
EP81
EPD - 69-81
A1 - Jin-Fu Li,
A1 - Hsin-Jung Huang,
A1 - Jeng-Bin Chen,
A1 - Chih-Pin Su,
A1 - Cheng-Wen Wu,
A1 - Chuang Cheng,
A1 - Shao-I Chen,
A1 - Chi-Yi Hwang,
A1 - Hsiao-Ping Lin,
PY - 2002
VL - 22
JA - IEEE Micro
ER -
 

Integrating reusable cores from multiple sources is essential in system-on-a-chip design. The authors present a hierarchical methodology for testing these cores and the integrated system chip.

Citation:
Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin, "A Hierarchical Test Methodology for Systems on Chip," IEEE Micro, vol. 22, no. 5, pp. 69-81, Sep./Oct. 2002, doi:10.1109/MM.2002.1044301
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