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2009
Issue No. 4 - July/August
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IEEE Design and Test of Computers
July/August 2009 (vol. 26 no. 4)
ISSN: 0740-7475
Table of Contents
Departments
From the EIC: Building and verifying hardware at a higher level of abstraction
(Abstract)
pp. 2
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Editorial
Call for Papers
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pp. 3
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Special Issue
Guest Editors' Introduction: Raising the Abstraction Level of Hardware Design
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Philippe Coussy
, Université de Bretagne-Sud
Andres Takach
, Mentor Graphics
pp. 4-6
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An Introduction to High-Level Synthesis
(Abstract)
Philippe Coussy
, Université de Bretagne-Sud, Lab-STICC
Daniel D. Gajski
, University of California
Michael Meredith
, Forte Design Systems
Andres Takach
, Mentor Graphics
pp. 8-17
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High-Level Synthesis: Past, Present, and Future
(Abstract)
Grant Martin
, Tensilica
Gary Smith
, Gary Smith EDA
pp. 18-25
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Virtual Roundtable: User Perspectives
(Abstract)
pp. 26-33
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Lessons and Experiences with High-Level Synthesis
(Abstract)
Soujanna Sarkar
, Texas Instruments
Shashank Dabral
, Texas Instruments
Praveen K. Tiwari
, Interra Systems
Raj S. Mitra
, Texas Instruments
pp. 34-45
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High-Level Dataflow Transformations Using Taylor Expansion Diagrams
(Abstract)
Maciej Ciesielski
, University of Massachusetts, Amherst
Jeremie Guillot
, Lab-STICC, Université de Bretagne Sud, Lorient, France
Daniel Gomez-Prado
, University of Massachusetts, Amherst
Emmanuel Boutillon
, Lab-STICC, Université de Bretagne Sud, Lorient, France
pp. 46-57
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Hardware Coprocessor Synthesis from an ANSI C Specification
(Abstract)
Sumit Ahuja
, Virginia Polytechnic and State University
Swathi T. Gurumani
, CebaTech
Chad Spackman
, CebaTech
Sandeep K. Shukla
, Virginia Polytechnic and State University
pp. 58-67
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Subword Switching Activity Minimization to Optimize Dynamic Power Consumption
(Abstract)
María Carmen Molina
, Complutense University of Madrid
Rafael Ruiz-Sautua
, Complutense University of Madrid
Alberto Del Barrio
, Complutense University of Madrid
José Manuel Mendías
, Complutense University of Madrid
pp. 68-77
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Statistical High-Level Synthesis under Process Variability
(Abstract)
Yuan Xie
, Pennsylvania State University
Yibo Chen
, Pennsylvania State University
pp. 78-87
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Functional Equivalence Verification Tools in High-Level Synthesis Flows
(Abstract)
Anmol Mathur
, Calypto Design Systems
Masahiro Fujita
, University of Tokyo
Edmund Clarke
, Carnegie Mellon University
Pascal Urard
, STMicroelectronics
pp. 88-95
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CEDA Currents
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pp. 96-98
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Design Automation Technical Committee Newsletter
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pp. 99
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Book Review: A physical-design picture book
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Igor Markov
, University of Michigan
pp. 100-101
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Test Technology TC Newsletter
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pp. 102-103
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The Last Byte: The HLS tipping point
(Abstract)
Jason Cong
, University of California, Los Angeles
Wolfgang Rosenstiel
, Eberhard Karls Universität Tübingen
pp. 104
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