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Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses
January/February 2004 (vol. 21 no. 1)
pp. 56-63
ASCII Text
x 
 
Naran Sirisantana, Kaushik Roy, "Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses," IEEE Design & Test of Computers, vol. 21, no. 1, pp. 56-63, January/February, 2004.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2004.1261850,
author = {Naran Sirisantana and Kaushik Roy},
title = {Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses},
journal ={IEEE Design & Test of Computers},
volume = {21},
number = {1},
issn = {0740-7475},
year = {2004},
pages = {56-63},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2004.1261850},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses
IS - 1
SN - 0740-7475
SP56
EP63
EPD - 56-63
A1 - Naran Sirisantana,
A1 - Kaushik Roy,
PY - 2004
VL - 21
JA - IEEE Design & Test of Computers
ER -
 
Kaushik Roy, Purdue University

Two CMOS design techniques use dual threshold voltages to reduce power consumption while maintaining high performance. Simulation results show power savings of 21% for one technique at low activity, and for the other, 19% at high activity and 38% at low activity.

Citation:
Naran Sirisantana, Kaushik Roy, "Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses," IEEE Design & Test of Computers, vol. 21, no. 1, pp. 56-63, Jan.-Feb. 2004, doi:10.1109/MDT.2004.1261850
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