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Automating Wave-Pipelined Circuit Design
November/December 2003 (vol. 20 no. 6)
pp. 51-58
ASCII Text
x 
 
Woo Jin Kim, Yong-Bin Kim, "Automating Wave-Pipelined Circuit Design," IEEE Design and Test of Computers, vol. 20, no. 6, pp. 51-58, November/December, 2003.
 
 
BibTex
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@article{ 10.1109/MDT.2003.1246164,
author = {Woo Jin Kim and Yong-Bin Kim},
title = {Automating Wave-Pipelined Circuit Design},
journal ={IEEE Design and Test of Computers},
volume = {20},
number = {6},
issn = {0740-7475},
year = {2003},
pages = {51-58},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1246164},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Automating Wave-Pipelined Circuit Design
IS - 6
SN - 0740-7475
SP51
EP58
EPD - 51-58
A1 - Woo Jin Kim,
A1 - Yong-Bin Kim,
PY - 2003
VL - 20
JA - IEEE Design and Test of Computers
ER -
 
Woo Jin Kim, Sun Microsystems
Yong-Bin Kim, Northeastern University

Wave pipelining offers faster clock rates than conventional pipelining; however, wave-pipelined circuit design is time-consuming and requires a high level of expertise. By augmenting a commercial tool with delay-balancing scripts, this method automates the synthesis part of the process with minimal delay deviation.

Citation:
Woo Jin Kim, Yong-Bin Kim, "Automating Wave-Pipelined Circuit Design," IEEE Design and Test of Computers, vol. 20, no. 6, pp. 51-58, Nov./Dec. 2003, doi:10.1109/MDT.2003.1246164
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