Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors

Design&Test
2003
Issue No. 6 - November/December
Abstract - Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors

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November/December 2003 (vol. 20 no. 6)

pp. 18-24

	ASCII Text	x
	Stephen H. Unger, "Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors," IEEE Design and Test of Computers, vol. 20, no. 6, pp. 18-24, November/December, 2003.

	BibTex	x
	@article{ 10.1109/MDT.2003.1246160, author = {Stephen H. Unger}, title = {Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors}, journal ={IEEE Design and Test of Computers}, volume = {20}, number = {6}, issn = {0740-7475}, year = {2003}, pages = {18-24}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1246160}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors IS - 6 SN - 0740-7475 SP18 EP24 EPD - 18-24 A1 - Stephen H. Unger, PY - 2003 VL - 20 JA - IEEE Design and Test of Computers ER -

Stephen H. Unger, Columbia University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1246160

Editor's note: For certain asynchronous logic circuits, it's possible to reduce transistor channels at no operational cost. This technique systematically increases speed while reducing both chip area and energy dissipation. It can also improve testability. For dynamic operation, it's possible to eliminate a transistor altogether without any negative effects.

—Fabrizio Lombardi, Northeastern University

Citation:

Stephen H. Unger, "Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors," IEEE Design and Test of Computers, vol. 20, no. 6, pp. 18-24, Nov./Dec. 2003, doi:10.1109/MDT.2003.1246160

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