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Three Generations of Asynchronous Microprocessors
November/December 2003 (vol. 20 no. 6)
pp. 9-17
ASCII Text
x 
 
Alain J. Martin, Mika Nystr?, Catherine G. Wong, "Three Generations of Asynchronous Microprocessors," IEEE Design and Test of Computers, vol. 20, no. 6, pp. 9-17, November/December, 2003.
 
 
BibTex
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@article{ 10.1109/MDT.2003.1246159,
author = {Alain J. Martin and Mika Nystr? and Catherine G. Wong},
title = {Three Generations of Asynchronous Microprocessors},
journal ={IEEE Design and Test of Computers},
volume = {20},
number = {6},
issn = {0740-7475},
year = {2003},
pages = {9-17},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1246159},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Three Generations of Asynchronous Microprocessors
IS - 6
SN - 0740-7475
SP9
EP17
EPD - 9-17
A1 - Alain J. Martin,
A1 - Mika Nystr?,
A1 - Catherine G. Wong,
PY - 2003
VL - 20
JA - IEEE Design and Test of Computers
ER -
 
Alain J. Martin, California Institute of Technology
Mika Nystr?, California Institute of Technology
Catherine G. Wong, California Institute of Technology

Editor's note:This article traces the evolution of Caltech asynchronous processors from a simple proof of concept, to a high-performance MIPS-like processor using a different buffer circuit for better performance, to the latest 8051 clone targeting low-energy operation. The authors describe the control aspects of the evolving circuit styles.

—Yong-Bin Kim, Northeastern University

Citation:
Alain J. Martin, Mika Nystr?, Catherine G. Wong, "Three Generations of Asynchronous Microprocessors," IEEE Design and Test of Computers, vol. 20, no. 6, pp. 9-17, Nov./Dec. 2003, doi:10.1109/MDT.2003.1246159
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