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Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings
September/October 2003 (vol. 20 no. 5)
pp. 84-89
ASCII Text
x 
 
Peter C. Maxwell, "Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings," IEEE Design and Test of Computers, vol. 20, no. 5, pp. 84-89, September/October, 2003.
 
 
BibTex
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@article{ 10.1109/MDT.2003.1232260,
author = {Peter C. Maxwell},
title = {Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings},
journal ={IEEE Design and Test of Computers},
volume = {20},
number = {5},
issn = {0740-7475},
year = {2003},
pages = {84-89},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1232260},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings
IS - 5
SN - 0740-7475
SP84
EP89
EPD - 84-89
A1 - Peter C. Maxwell,
PY - 2003
VL - 20
JA - IEEE Design and Test of Computers
ER -
 
Peter C. Maxwell, Agilent Technologies

Editor's note:
For years, it has been common to run a test at wafer and then exactly thesame test again at package. This article shows how one company took adetailed look at the wafer/package test mix and adjusted it to reduce costwhile retaining quality.
—Rob Aitken, Artisan Components

Citation:
Peter C. Maxwell, "Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings," IEEE Design and Test of Computers, vol. 20, no. 5, pp. 84-89, Sep./Oct. 2003, doi:10.1109/MDT.2003.1232260
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