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Embedded Deterministic Test for Low-Cost Manufacturing
September/October 2003 (vol. 20 no. 5)
pp. 58-66
Janusz Rajski, Mentor Graphics
Mark Kassab, Mentor Graphics
Nilanjan Mukherjee, Mentor Graphics
Nagesh Tamarapalli, Mentor Graphics
Jerzy Tyszer, Poznan University of Technology
Jun Qian, Cisco Systems

Editor's note:
You have probably heard that BIST takes too long and its fault coverage is low, and that deterministic test requires too many patterns. This article shows how on-chip compression and decompression techniques can provide high fault coverage with low test times.
—Rob Aitken, Artisan Components

Citation:
Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian, "Embedded Deterministic Test for Low-Cost Manufacturing," IEEE Design and Test of Computers, vol. 20, no. 5, pp. 58-66, Sep./Oct. 2003, doi:10.1109/MDT.2003.1232257
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