A Hierarchical Infrastructure for SoC Test Management

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July/August 2003 (vol. 20 no. 4)

pp. 32-39

	ASCII Text	x
	Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian, "A Hierarchical Infrastructure for SoC Test Management," IEEE Design and Test of Computers, vol. 20, no. 4, pp. 32-39, July/August, 2003.

	BibTex	x
	@article{ 10.1109/MDT.2003.1214350, author = {Alfredo Benso and Stefano Di Carlo and Paolo Prinetto and Yervant Zorian}, title = {A Hierarchical Infrastructure for SoC Test Management}, journal ={IEEE Design and Test of Computers}, volume = {20}, number = {4}, issn = {0740-7475}, year = {2003}, pages = {32-39}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1214350}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - A Hierarchical Infrastructure for SoC Test Management IS - 4 SN - 0740-7475 SP32 EP39 EPD - 32-39 A1 - Alfredo Benso, A1 - Stefano Di Carlo, A1 - Paolo Prinetto, A1 - Yervant Zorian, PY - 2003 VL - 20 JA - IEEE Design and Test of Computers ER -

Alfredo Benso, Politecnico di Torino

Stefano Di Carlo, Politecnico di Torino

Paolo Prinetto, Politecnico di Torino

Yervant Zorian, Virage Logic

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1214350

HD2BIST?a complete hierarchical framework for BIST scheduling, data-patterns delivery, and diagnosis of complex systems?maximizes and simplifies the reuse of built-in test architectures. HD2BIST optimizes flexibility for chip designers planning an overall SoC test strategy by defining a test access method that provides direct virtual access to each core of the system.

Citation:

Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian, "A Hierarchical Infrastructure for SoC Test Management," IEEE Design and Test of Computers, vol. 20, no. 4, pp. 32-39, July/Aug. 2003, doi:10.1109/MDT.2003.1214350

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