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Clock and Power Gating with Timing Closure
May/June 2003 (vol. 20 no. 3)
pp. 32-39
ASCII Text
x 
 
Arindam Mukherjee, Malgorzata Marek-Sadowska, "Clock and Power Gating with Timing Closure," IEEE Design and Test of Computers, vol. 20, no. 3, pp. 32-39, May/June, 2003.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2003.1198683,
author = {Arindam Mukherjee and Malgorzata Marek-Sadowska},
title = {Clock and Power Gating with Timing Closure},
journal ={IEEE Design and Test of Computers},
volume = {20},
number = {3},
issn = {0740-7475},
year = {2003},
pages = {32-39},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1198683},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Clock and Power Gating with Timing Closure
IS - 3
SN - 0740-7475
SP32
EP39
EPD - 32-39
A1 - Arindam Mukherjee,
A1 - Malgorzata Marek-Sadowska,
PY - 2003
VL - 20
JA - IEEE Design and Test of Computers
ER -
 
Arindam Mukherjee, University of North Carolina at Charlotte
Malgorzata Marek-Sadowska, University of California, Santa Barbara

Editor?s note:

Assuming that delay is linearly dependent on local power supply voltage, the authors show how to set up an analysis to determine the effect of power supply variations on delay. This analysis can drive the introduction of clock gating, an increasingly popular technique for reducing dynamic power dissipation.
--Sani R. Nassif, IBM Austin Research Laboratory

Citation:
Arindam Mukherjee, Malgorzata Marek-Sadowska, "Clock and Power Gating with Timing Closure," IEEE Design and Test of Computers, vol. 20, no. 3, pp. 32-39, May/June 2003, doi:10.1109/MDT.2003.1198683
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