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Fast Fault Simulation for Nonlinear Analog Circuits
March/April 2003 (vol. 20 no. 2)
pp. 40-47
ASCII Text
x 
 
Nur Engin, Hans G. Kerkhoff, "Fast Fault Simulation for Nonlinear Analog Circuits," IEEE Design and Test of Computers, vol. 20, no. 2, pp. 40-47, March/April, 2003.
 
 
BibTex
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@article{ 10.1109/MDT.2003.1188261,
author = {Nur Engin and Hans G. Kerkhoff},
title = {Fast Fault Simulation for Nonlinear Analog Circuits},
journal ={IEEE Design and Test of Computers},
volume = {20},
number = {2},
issn = {0740-7475},
year = {2003},
pages = {40-47},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1188261},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Fast Fault Simulation for Nonlinear Analog Circuits
IS - 2
SN - 0740-7475
SP40
EP47
EPD - 40-47
A1 - Nur Engin,
A1 - Hans G. Kerkhoff,
PY - 2003
VL - 20
JA - IEEE Design and Test of Computers
ER -
 
Nur Engin, Philips Research Laboratories
Hans G. Kerkhoff, MESA+ Research Institute

A new method of transient fault simulation uses dc bias grouping of faulty circuits and decreases the number of Newton-Raphson iterations needed to reach a solution. An experimental tool implementing this method achieves a speedup of 20% to 30% on a flat netlist.

Citation:
Nur Engin, Hans G. Kerkhoff, "Fast Fault Simulation for Nonlinear Analog Circuits," IEEE Design and Test of Computers, vol. 20, no. 2, pp. 40-47, Mar./Apr. 2003, doi:10.1109/MDT.2003.1188261
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