Instruction Scheduler Generation for Retargetable Compilation

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January/February 2003 (vol. 20 no. 1)

pp. 34-41

	ASCII Text	x
	Oliver Wahlen, Manuel Hohenauer, Rainer Leupers, Heinrich Meyr, "Instruction Scheduler Generation for Retargetable Compilation," IEEE Design and Test of Computers, vol. 20, no. 1, pp. 34-41, January/February, 2003.

	BibTex	x
	@article{ 10.1109/MDT.2003.1173051, author = {Oliver Wahlen and Manuel Hohenauer and Rainer Leupers and Heinrich Meyr}, title = {Instruction Scheduler Generation for Retargetable Compilation}, journal ={IEEE Design and Test of Computers}, volume = {20}, number = {1}, issn = {0740-7475}, year = {2003}, pages = {34-41}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1173051}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Instruction Scheduler Generation for Retargetable Compilation IS - 1 SN - 0740-7475 SP34 EP41 EPD - 34-41 A1 - Oliver Wahlen, A1 - Manuel Hohenauer, A1 - Rainer Leupers, A1 - Heinrich Meyr, PY - 2003 VL - 20 JA - IEEE Design and Test of Computers ER -

Oliver Wahlen, Aachen University of Technology

Manuel Hohenauer, Aachen University of Technology

Rainer Leupers, Aachen University of Technology

Heinrich Meyr, Aachen University of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1173051

The availability of C compilers is crucial to the efficient design of embedded systems. Using virtual resources to automatically generate parts of a compiler's instruction scheduler from a formal processor description significantly reduces the overall scheduler generation time.

Citation:

Oliver Wahlen, Manuel Hohenauer, Rainer Leupers, Heinrich Meyr, "Instruction Scheduler Generation for Retargetable Compilation," IEEE Design and Test of Computers, vol. 20, no. 1, pp. 34-41, Jan./Feb. 2003, doi:10.1109/MDT.2003.1173051

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