Compilation Approach for Coarse-Grained Reconfigurable Architectures January/February 2003 (vol. 20 no. 1) pp. 26-33
Coarse-grained reconfigurable architectures can enhance the performance of critical loops and computation-intensive functions. Such architectures need efficient compilation techniques to map algorithms onto customized architectural configurations. A new compilation approach uses a generic reconfigurable architecture to tackle the memory bottleneck that typically limits the performance of many applications.
Citation:
Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt, "Compilation Approach for Coarse-Grained Reconfigurable Architectures," IEEE Design and Test of Computers, vol. 20, no. 1, pp. 26-33, Jan./Feb. 2003, doi:10.1109/MDT.2003.1173050 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||