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NOVEMBER/DECEMBER 2002 (Vol. 19, No. 6) pp. 110-119
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2002 Annual Index, Volume 19
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"2002 IEEE Design & Test of Computers Annual Index, Volume 19," IEEE DESIGN & TEST, Vol. 19, 06, pp. 110-119, NOVEMBER/DECEMBER, 2002.
 
 
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@article{ 10.1109/MDT.2002.10042,

author = {},

title = {2002 IEEE Design & Test of Computers Annual Index, Volume 19},

journal ={IEEE DESIGN & TEST},

volume = {19},

number = {06}

issn = {0740-7475},

year = {2002},

pages = {110-119},

doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2002.10042},

publisher = {IEEE Computer Society},

address = {Los Alamitos, CA, USA},

}
 
 
RefWorks Procite/RefMan/Endnote
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TY - MGZN

JO - IEEE DESIGN & TEST

TI - 2002 IEEE Design & Test of Computers Annual Index, Volume 19

IS - 06

SN - 0740-7475

SP - 110

EP - 119

PY - 2002

VL - 19

JA - IEEE DESIGN & TEST

ER -

 
This index includes all items appearing in this periodical during 2002 that are considered to have archival value. (The item title is listed only under the primary author entry in the author index.)

AUTHOR INDEX

A

Aitken, R.,and D. Wheater, "Guest Editors' Introduction: Stressing the Fundamentals," Special ITC Section, Sept.-Oct. 02, pp. 5-7.

Aktouf, C.,"A Complete Strategy for Testing an On-Chip Multiprocessor Architecture," Jan.-Feb. 02, pp. 18-28.

Aragonès, X.,et al.,"Noise Generation and Coupling Mechanisms in Deep-Submicron ICs," Sept.-Oct. 02, pp. 27-35.

Ashenden, P.J.,"Verilog and Other Standards," Standards, Jan.-Feb. 02, pp. 84-85.

Ashenden, P.J.,"The IEEE Standards Process," Standards, Mar.-Apr. 02, pp. 72-73.

Ashenden, P.J.,"What Makes a Good Standard?" Standards, May-June 02, p. 114.

Azaïs, F., see Renovell, M., Nov.-Dec. 02, pp. 83-89.

B

Barnhart, C.,et al., "Extending OPMISR beyond 10x Scan Test Efficiency," Sept.-Oct. 02, pp. 65-73.

Bayraktaroglu, I.,and A. Orailoglu, "Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST," Jan.-Feb. 02, pp. 42-53.

Benini, L., see Dalpasso, M., Sept.-Oct. 02, pp. 92-104.

Benso, A.,S. Chiusano, and P. Prinetto, "DFT and BIST of a Multichip Module for High-Energy Physics Experiments," May-June 02, pp. 94-105.

Bensoudane, E., see Paulin, P., Nov.-Dec. 02, pp. 17-26.

Bertrand, Y., see Renovell, M., Nov.-Dec. 02, pp. 83-89.

Blaauw, D.,and L. Lavagno, "Guest Editors' Introduction: Hot Topics at This Year's Design Automation Conference," Special DAC Section, July-Aug. 02, pp. 72-73.

Blanton, R.D., see Nag, P.K., Jan.-Feb. 02, pp. 29-41.

Blough, D., see Mooney, V., Nov.-Dec. 02, pp. 44-51.

Bogliolo, A., see Dalpasso, M., Sept.-Oct. 02, pp. 92-104.

Bordelon, J.,et al., "A Strategy for Mixed-Signal Yield Improvement," May-June 02, pp. 14-23.

Breant, F., see Liem, C., Nov.-Dec. 02, pp. 27-35.

Brunkhorst, V., see Barnhart, C., Sept.-Oct. 02, pp. 65-73.

Buchenrieder, K.J., see Schulz, S., Mar.-Apr. 02, pp. 60-69.

C

Cai, Y.,B. Laquai, and K. Luehman, "Jitter Testing for Gigabit Serial Communication Transceivers," Jan.-Feb. 02, pp. 66-74.

Caldwell, A.E.,A.B. Kahng, and I.L. Markov, "Toward CAD-IP Reuse: A Web Bookshelf of Fundamental Algorithms," May-June 02, pp. 72-81.

Castágne, J., see Rudack, M., Jan.-Feb. 02, pp. 6-17.

Cesário, W.,et al., "Multiprocessor SoC Platforms: A Component-Based Design Approach," Nov.-Dec. 02, pp. 52-63.

Chang, N., see Shin, D., July-Aug. 02, pp. 7-17.

Chen, L., see Krstic, A., July-Aug. 02, pp. 18-27.

Cheng, K.-T., see Krstic, A., July-Aug. 02, pp. 18-27.

Chen, H.-M., see Huang, I.-J., July-Aug. 02, pp. 28-38.

Chen, Z.,et al., " I DDQ Testing for Deep-Submicron ICs: Challenges and Solutions," Mar.-Apr. 02, pp. 24-33.

Chiusano, S., see Benso, A., May-June 02, pp. 94-105.

Chowdhary, A.,and R. Gupta, "A Methodology for Synthesis of Data Path Circuits," Nov.-Dec. 02, pp. 90-100.

Coitinho, R.M., see Galup-Montoro, C., Mar.-Apr. 02, pp. 50-58.

Cota, K., see Daasch, W., Sept.-Oct. 02, pp. 74-81.

Craig, M., see Bordelon, J., May-June 02, pp. 14-23.

D

Daasch, R., see Keshavarzi, A., Sept.-Oct. 02, pp. 36-43.

Daasch, W.,et al., "Neighborhood Selection for I DDQ Outlier Screening at Wafer Sort," Sept.-Oct. 02, pp. 74-81.

Dalpasso, M.,A. Bogliolo, and L. Benini, "Virtual Simulation of Distributed IP-Based Designs," Sept.-Oct. 02, pp. 92-104.

De, V., see Keshavarzi, A., Sept.-Oct. 02, pp. 36-43.

Dey, S., see Krstic, A., July-Aug. 02, pp. 18-27.

Dey, S., see Lahiri, K., July-Aug. 02, pp. 118-130.

Diaz-Nava, M., see Cesário, W., Nov.-Dec. 02, pp. 52-63.

Dill, D.L., see Shimizu, K., July-Aug. 02, pp. 96-106.

Distler, F., see Barnhart, C., Sept.-Oct. 02, pp. 65-73.

Dupont, E.,M. Nicolaidis, and P. Rohr, "Embedded Robustness IPs for Transient-Error-Free ICs," May-June 02, pp. 56-70.

F

Farnsworth, O., see Barnhart, C., Sept.-Oct. 02, pp. 65-73.

Favalli, M.,and C. Metra, "Online Testing Approach for Very Deep-Submicron ICs," Mar.-Apr. 02, pp. 16-23.

Ferko, A., see Barnhart, C., Sept.-Oct. 02, pp. 65-73.

G

Galup-Montoro, C.,M.C. Schneider, and R.M. Coitinho, "Resizing Rules for MOS Analog-Design Reuse," Mar.-Apr. 02, pp. 50-58.

Gangwal, O.P., see Rutten, M.J., July-Aug. 02, pp. 39-50.

Gattiker, A., see Nag, P.K., Jan.-Feb. 02, pp. 29-41.

Gauthier, L., see Cesário, W., Nov.-Dec. 02, pp. 52-63.

Ghosh, S., see McLaurin, T., May-June 02, pp. 8-13.

Girard, P.,"Survey of Low-Power Testing of VLSI Circuits," May-June 02, pp. 82-92.

Girard, P.,et al., "High Defect Coverage with Low-Power Test Sequences in a BIST Environment," Sept.-Oct. 02, pp. 44-52.

González, J., see Aragonès, X., Sept.-Dec. 02, pp. 27-35.

Gupta, R.,"Deep-Submicron Challenges," From the EIC, Mar.-Apr. 02, p. 3.

Gupta, R., see Chowdhary, A., Nov.-Dec. 02, pp. 90-100.

H

Hawkins, C., see Keshavarzi, A., Sept.-Oct. 02, pp. 36-43.

Hilgenstock, J., see Rudack, M., Jan.-Feb. 02, pp. 6-17.

Hsiao, M.S., see Sheng, S., Sept.-Oct. 02, pp. 56-64.

Huang, C.-J.,C.-F. Wu, and C.-C. Wang, "Image Processing Techniques for Wafer Defect Cluster Identification," Mar.-Apr. 02, pp. 44-48.

Huang, I.-J.,et al., "A Retargetable Embedded In-Circuit Emulation Module for Microprocessors," July-Aug. 02, pp. 28-38.

Huertas, G.,et al., "Practical Oscillation-Based Test of Integrated Filters," Nov.-Dec. 02, pp. 64-72.

Huertas, G.,et al., "Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell," Nov.-Dec. 02, pp. 73-82.

Huertas, J., see Huertas, G., Nov.-Dec. 02, pp. 64-72.

Huertas, J., see Huertas, G., Nov.-Dec. 02, pp. 73-82.

I

Ivanov, A., see Tabatabaei, S., May-June 02, pp. 24-36.

J

Jadhav, S., see Liem, C., Nov.-Dec. 02, pp. 27-35.

Jaspers, E.G.T., see Rutten, M.J., July-Aug. 02, pp. 39-50.

Jerraya, A., see Cesário, W., Nov.-Dec. 02, pp. 52-63.

Jin, Y., see Mihal, A., Nov.-Dec. 02, pp. 6-16.

Joo, Y., see Shin, D., July-Aug. 02, pp. 7-17.

Juan, C.-N., see Huang, I.-J., July-Aug. 02, pp. 28-38.

K

Kahng, A.B.,"The Cost of Design," The Road Ahead, July-Aug. 02, pp. 136,135.

Kahng, A.B.,"The Significance of Packaging," The Road Ahead, Nov.-Dec. 02, pp. 104-105.

Kahng, A.B.,"Variability," The Road Ahead, May-June 02, pp. 120,116.

Kahng, A.B., see Caldwell, A.E., May-June 02, pp. 72-81.

Kao, C.-F., see Ing-Jer Huang, July-Aug. 02, pp. 28-38.

Keller, B., see Barnhart, C., Sept.-Oct. 02, pp. 65-73.

Keshavarzi, A., see Chen, Z., Mar.-Apr. 02, pp. 24-33.

Keshavarzi, A.,et al., "Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits," Sept.-Oct. 02, pp. 36-43.

Keutzer, K., see Mihal, A., Nov.-Dec. 02, pp. 6-16.

Kim, J., see Shin, D., July-Aug. 02, pp. 7-17.

Koenemann, B., see Barnhart, C., Sept.-Oct. 02, pp. 65-73.

Kondratyev, A.,and K. Lwin, "Design of Asynchronous Circuits Using Synchronous CAD Tools," July-Aug. 02, pp. 107-117.

Krstic, A.,et al., "Embedded Software-Based Self-Test for Programmable Core-Based Designs," July-Aug. 02, pp. 18-27.

Kulkarni, C., see Mihal, A., Nov.-Dec. 02, pp. 6-16.

Kumar Goel, S., see Vermeulen, B., May-June 02, pp. 37-45.

L

Lahiri, K.,S. Dey, and A. Raghunathan, "Communication-Based Power Management," July-Aug. 02, pp. 118-130.

Lai, W.-C., see Krstic, A., July-Aug. 02, pp. 18-27.

Landrault, C., see Girard, P., Sept.-Oct. 02, pp. 44-52.

Laquai, B., see Cai, Y., Jan.-Feb. 02, pp. 66-74.

Lavagno, L., see Blaauw, D., July-Aug. 02, pp. 72-73.

Leupers, R.,"Compiler Design Issues for Embedded Processors," July-Aug. 02, pp. 51-58.

Levia, O., see Liem, C., Nov.-Dec. 02, pp. 27-35.

Liem, C.,et al., "Embedded Tools for a Configurable and Customizable DSP Architecture," Nov.-Dec. 02, pp. 27-35.

Lombardi, F., see Zhao, J., Jan.-Feb. 02, pp. 54-64.

Luehman, K., see Cai, Y., Jan.-Feb. 02, pp. 66-74.

Lu, T.-A., see Huang, I.-J., July-Aug. 02, pp. 28-38.

Lwin, K., see Kondratyev, A., July-Aug. 02, pp. 107-117.

Lyonnard, D., see Cesário, W., Nov.-Dec. 02, pp. 52-63.

M

Madangarli, V., see Bordelon, J., May-June 02, pp. 14-23.

Madge, R., see Daasch, W., Sept.-Oct. 02, pp. 74-81.

Magarshack, P.,"Improving SoC Design Quality through a Reproducible Design Flow," Jan.-Feb. 02, pp. 76-83.

Malik, S., see Mihal, A., Nov.-Dec. 02, pp. 6-16.

Maly, W., see Nag, P.K., Jan.-Feb. 02, pp. 29-41.

Markov, I.L., see Caldwell, A.E., May-June 02, pp. 72-81.

Martin, G.,"Guest Editor's Introduction: The Reuse of Complex Architectures," Nov.-Dec. 02, pp. 4-5.

Marwedel, P.,"Guest Editor's Introduction: Processor-Based Designs," July-Aug. 02, pp. 5-6.

Maxwell, P., see Segura, J., Sept.-Oct. 02, pp. 5-7.

McLaurin, T.,and S. Ghosh, "ETM10 Incorporates Hardware Segment of IEEE P1500," May-June 02, pp. 8-13.

McNames, J., see Daasch, W., Sept.-Oct. 02, pp. 74-81.

Metra, C., see Favalli, M., Mar.-Apr. 02, pp. 16-23.

Meyer, F.J., see Jun Zhao, Jan.-Feb. 02, pp. 54-64.

Mihal, A.,et al., "Developing Architectural Platforms: A Disciplined Approach," Nov.-Dec. 02, pp. 6-16.

Moch, S., see Rudack, M., Jan.-Feb. 02, pp. 6-17.

Moll, F., see Aragonès, X., Sept.-Oct.. 02, pp. 27-35.

Mooney, V.,and D. Blough, "A Hardware-Software Real-Time Operating System Framework for SoCs," Nov.-Dec. 02, pp. 44-51.

Moskewicz, M., see Mihal, A., Nov.-Dec. 02, pp. 6-16.

Müller, D., see Siegmund, R., July-Aug. 02, pp. 84-95.

N

Nag, P.K.,et al., "Modeling the Economics of Testing: A DFT Perspective," Jan.-Feb. 02, pp. 29-41.

Narendra, S., see Keshavarzi, A., Sept.-Oct. 02, pp. 36-43.

Nicolaidis, M., see Dupont, E., May-June 02, pp. 56-70.

Nicolescu, G., see Cesário, W., Nov.-Dec. 02, pp. 52-63.

O

O'Farrell, R., see Liem, C., Nov.-Dec. 02, pp. 27-35.

Olgaard, C., see Ozev, S., Sept.-Oct. 02, pp. 82-91.

Onodera, T., see Barnhart, C., Sept.-Oct. 02, pp. 65-73.

Orailoglu, A., see Bayraktaroglu, I., Jan.-Feb. 02, pp. 42-53.

Orailoglu, A., see Ozev, S., Sept.-Oct. 02, pp. 82-91.

Ozev, S.,C. Olgaard, and A. Orailoglu, "Multilevel Testability Analysis and Solutions for Integrated Bluetooth Transceivers," Sept.-Oct. 02, pp. 82-91.

P

Pateras, S.,"IP for Embedded Diagnosis," May-June 02, pp. 46-55.

Paulin, P.,C. Pilkington, and E. Bensoudane, "StepNP: A System-Level Exploration Platform for Network Processors," Nov.-Dec. 02, pp. 17-26.

Paulin, P.G.,and M. Santana, "FlexWare: A Retargetable, Embedded-Software Development Environment," July-Aug. 02, pp. 59-69.

Paviot, Y., see Cesário, W., Nov.-Dec. 02, pp. 52-63.

Peralías, E., see Huertas, G., Nov.-Dec. 02, pp. 64-72.

Peralías, E., see Huertas, G., Nov.-Dec. 02, pp. 73-82.

Perrott, M.H.,"Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL Circuits," July-Aug. 02, pp. 74-83.

Pilkington, C., see Paulin, P., Nov.-Dec. 02, pp. 17-26.

Pineda de Gyvez, J., see Rodríguez Montañés, P., Sept.-Oct. 02, pp. 18-26.

Pol, E.-J.D., see Rutten, M.J., July-Aug. 02, pp. 39-50.

Pravossoudovitch, S., see Girard, P., Sept.-Oct. 02, pp. 44-52.

Prinetto, P., see Benso, A., May-June 02, pp. 94-105.

R

Raghunathan, A., see Lahiri, K., July-Aug. 02, pp. 118-130.

Redeker, M., see Rudack, M., Jan.-Feb. 02, pp. 6-17.

Renovell, M.,F. Azais, and Y. Bertrand, "Improving Defect Detection in Static-Voltage Testing," Nov.-Dec. 02, pp. 83-89.

Rodríguez Montañés, R.,P. Volf, and J. Pineda de Gyvez, "Resistance Characterization for Weak Open Defects," Sept.-Oct. 02, pp. 18-26.

Rohr, P., see Dupont, E., May-June 02, pp. 56-70.

Roy, K., see Chen, Z., Mar.-Apr. 02, pp. 24-33.

Roy, K., see Keshavarzi, A., Sept.-Oct. 02, pp. 36-43.

Rozenblit, J.W., see Schulz, S., Mar.-Apr. 02, pp. 60-69.

Rubio, A., see Aragonès, X., Sept.-Oct. 02, pp. 27-35.

Rudack, M.,et al., "A Large-Area Integrated Multiprocessor System for Video Applications," Jan.-Feb. 02, pp. 6-17.

Rueda, A., see Huertas, G., Nov.-Dec. 02, pp. 64-72.

Rueda, A., see Huertas, G., Nov.-Dec. 02, pp. 73-82.

Rutten, M.J.,et al., "A Heterogeneous Multiprocessor Architecture for Flexible Media Processing," July-Aug. 02, pp. 39-50.

Ryan, R., see Liem, C., Nov.-Dec. 02, pp. 27-35.

S

Sabade, S, and D.M.H. Walker, " I DDQ Test: Will It Survive the DSM Challenge?" Sept.-Oct. 02, pp. 8-16.

Sachdev, M., see Keshavarzi, A., Sept.-Oct. 02, pp. 8-16.

Santana, M., see Paulin, P.G., July-Aug. 02, pp. 59-69.

Sauer, C., see Mihal, A., Nov.-Dec. 02, pp. 6-16.

Schneider, M.C., see Galup-Montoro, C., Mar.-Apr. 02, pp. 50-58.

Schulz, S.,K.J. Buchenrieder, and J.W. Rozenblit, "Multilevel Testing for Design Verification of Embedded Systems," Mar.-Apr. 02, pp. 60-69.

Scott, D., see Barnhart, C., Sept.-Oct. 02, pp. 65-73.

Segura, J.,and P. Maxwell, "Guest Editors' Introduction: Defect-Oriented Testing in the Deep-Submicron Era," Sept.-Oct. 02, pp. 5-7.

Shah, N., see Mihal, A., Nov.-Dec. 02, pp. 6-16.

Sheng, S.,and M. Hsiao, "Efficient Sequential Test Generation Based on Logic Simulation," Sept.-Oct. 02, pp. 56-64.

Shim, H., see Shin, D., July-Aug. 02, pp. 7-17.

Shimizu, K.,and D.L. Dill, "Using Formal Specifications for Functional Validation of Hardware Designs," July-Aug. 02, pp. 96-106.

Shin, D.,"Energy-Monitoring Tool for Low-Power Embedded Programs," July-Aug. 02, pp. 7-17.

Siegmund, R.,and D. Müller, "Automatic Synthesis of Communication Controller Hardware from Protocol Specifications," July-Aug. 02, pp. 84-95.

Silveira, L.M.,and N. Vargas, "Characterizing substrate coupling in deep-submicron designs," Mar.-Apr. 02, pp. 4-15.

Stan, M.R.,"CMOS Circuits with Subvolt Supply Voltages," Mar.-Apr. 02, pp. 34-43.

Stitt, G.,and F. Vahid, "Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic," Nov.-Dec. 02, pp. 36-43.

T

Tabatabaei, S.,and A. Ivanov, "Embedded Timing Analysis: A SoC Infrastructure," May-June 02, pp. 24-36.

Timmer, A., see Rutten, M.J., July-Aug. 02, pp. 39-50.

Tranchina, B., see Bordelon, J., May-June 02, pp. 14-23.

Tsai, M., see Mihal, A., Nov.-Dec. 02, pp. 6-16.

Tschanz, J., see Keshavarzi, A., Sept.-Oct. 02, pp. 36-43.

V

Vahid, F., see Stitt, G., Nov.-Dec. 02, pp. 36-43.

van der Wolf, P., see Rutten, M.J., July-Aug. 02, pp. 39-50.

van Eijndhoven, J.T.J., see Rutten, M.J., July-Aug. 02, pp. 39-50.

Vargas, N., see Silveira, L.M., Mar.-Apr. 02, pp. 4-15.

Vázquez, D., see Huertas, G., Nov.-Dec. 02, pp. 64-72.

Vázquez, D., see Huertas, G., Nov.-Dec. 02, pp. 73-82.

Vermeulen, B.,and S. Kumar Goel, "Design for Debug: Catching Design Errors in Digital Chips," May-June 02, pp. 37-45.

Virazel, A., see Girard, P., Sept.-Oct. 02, pp. 44-52.

Vissers, K., see Mihal, A., Nov.-Dec. 02, pp. 6-16.

Volf, P., see Rodríguez Montañés, Sept.-Oct. 02, pp. 18-26.

W

Walker, D.M.H., see Sabade, S. Sept.-Oct. 02, pp. 8-16.

Wang, C.-C., see Huang, C.-J., Mar.-Apr. 02, pp. 44-48.

Weber, S., see Mihal, A., Nov.-Dec. 02, pp. 6-16.

Wei, L., see Chen, Z., Mar.-Apr. 02, pp. 24-33.

Wei, S., see Nag, P.K., Jan.-Feb. 02, pp. 29-41.

Wheater, D., see Aitken, R., Sept.-Oct. 02, pp. 54-55.

Wu, C.-F., see Huang, C.-J., Mar.-Apr. 02, pp. 44-48.

Wunderlich, H.J., see Girard, P., Sept.-Oct. 02, pp. 44-52.

Y

Yoo, S., see Cesário, W., Nov.-Dec. 02, pp. 52-63.

Yun, H.-S., see Shin, D., July-Aug. 02, pp. 7-17.

Z

Zhao, J.,F.J. Meyer, and F. Lombardi, "Analyzing and Diagnosing Interconnect Faults in Bus-Structured Systems," Jan.-Feb. 02, pp. 54-64.

Zorian, Y.,"Guest Editor's Introduction: What Is Infrastructure IP?" May-June 02, pp. 5-7.

SUBJECT INDEX

Analog circuits

deep-submicron challenges, From the EIC, Gupta, R., Mar.-Apr. 02, p. 3.

testing mixed-signal cores, practical oscillation-based test in analog macrocell, Huertas, G., et al., Nov.-Dec. 02, pp. 73-82.

Analog-digital conversion

mixed-signal, yield improvement strategy, Bordelon, J., et al., May-June 02, pp. 14-23.

Application-specific ICs

LHC high-energy phys, expts., MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.

Application-specific ICs,
see Mixed analog-digital ICs
Asynchronous circuits

synchronous, CAD tools, Kondratyev, A., et al., July-Aug. 02, pp. 107-117.

Automatic optical inspection

wafer defect cluster identification, image processing, Huang, C.-J., et al., Mar.-Apr. 02, pp. 44-48.

Automatic testing

very deep-submicron ICs, online testing approach, Favalli, M., et al., Mar.-Apr. 02, pp. 16-23.

Automatic testing,
see Automatic test-pattern generation, Automatic test software
Automatic test-pattern generation

ETM10 incorporates hardware segment of IEEE P1500, McLaurin, T., et al., May-June 02, pp. 8-13.

Automatic test software

wafer defect cluster identification, image processing, Huang, C.-J., et al., Mar.-Apr. 02, pp. 44-48.

Boundary scan testing

LHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.

Built-in safe test

high defect coverage with low-power test sequences in BIST environment, Girard, P., et al., Sept.-Oct. 02, pp. 44-52.

Built-in self-test

embedded software-based self-test for programmable, core-based designs, Krstic, A., et al., July-Aug. 02, pp. 18-27.

intellectual property for embedded diagnosis, Pateras, S., May-June 02, pp. 46-55.

large-area, integrated multiprocessor system for video coding, Rudack, M., et al., Jan.-Feb. 02, pp. 6-17.

LHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.

low-power VLSI circuit, testing, Girard, P., May-June 02, pp. 82-92.

scan-based BIST, rapid diagnosis, deterministic partitioning, Bayraktaroglu, I., et al., Jan.-Feb. 02, pp. 42-53.

CAD

design automation, special DAC section, July-Aug. 02, pp. 72-130.

design automation, guest editors' introduction, Blaauw, D., et al., July-Aug. 02, pp. 72-73.

CAD,
see Electronic design automation, Logic CAD
Calorimetry,
see Particle calorimetry
Cells (electric)

battery-driven system-level power management, Lahiri, K., et al., July-Aug. 02, pp. 118-130.

Circuit analysis computing,
see Circuit simulation
Circuit CAD

CAD-IP reuse, Web bookshelf of fundamental algorithms, Caldwell, A.E., et al., May-June 02, pp. 72-81.

Circuit CAD,
see Hardware description languages
Circuit layout,
see IC layout
Circuit simulation

CMOS circuits, with subvolt supply voltages, Stan, M.R., Mar.-Apr. 02, pp. 34-43.

fractional-N frequency, synthesizers, behavioral simulation, Perrott, M.H., July-Aug. 02, pp. 74-83.

scan-based BIST, rapid diagnosis, deterministic partitioning, Bayraktaroglu, I., et al., Jan.-Feb. 02, pp. 42-53.

Circuit testing

bus-structured systems, interconnect faults, analysis/diagnosis, Zhao, J., et al., Jan.-Feb. 02, pp. 54-64.

Circuit testing,
see IC testing
Circuit theory,
see Network synthesis, Network topology
Cluster tools

wafer defect cluster identification, image processing, Huang, C.-J., et al., Mar.-Apr. 02, pp. 44-48.

CMOS ICs

deep-submicron IC, I DDQ testing, Chen, Z., et al., Mar.-Apr. 02, pp. 24-33.

defect-oriented testing in the deep-submicron era, special issue, Sept.-Oct. 02, pp. 5-52.

defect-oriented testing in the deep-submicron era, guest editors' introduction, Segura, J., et al., Sept.-Oct. 02, pp. 5-7.

leakage and process variation effects in current testing on future CMOS circuits, Keshavarzi, A., et al., Sept.-Oct. 02, pp. 36-43.

subvolt supply voltages, Stan, M.R., Mar.-Apr. 02, pp. 34-43.

Colliding beam accelerators

LHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.

Computer applications,
see CAD
Computer architecture

disciplined approach to develop architectural platforms, Mihal, A., et al., Nov.-Dec. 02, pp. 6-16.

embedded tools for configurable and customizable DSP architecture, Liem, C., et al., Nov.-Dec. 02, pp. 27-35.

energy advantages of microprocessor platforms with on-chip configurable logic, Stitt, G., et al., Nov.-Dec. 02, pp. 36-43.

hardware-software real-time operating system framework for SoCs, Mooney, V., et al., Nov.-Dec. 02, pp. 44-51.

StepNP, system-level exploration platform for network processors, Paulin, P., et al., Nov.-Dec. 02, pp. 17-26.

Computer architecture,
see Parallel architectures, Reconfigurable architectures
Computer debugging

retargetable embedded in-circuit, emulation module for microprocessors, Huang, I.-J., et al., July-Aug. 02, pp. 28-38.

Computer interfaces,
see System buses
Computerized instrumentation,
see High-energy physics instrumentation computing
Computer testing

on-chip multiprocessor architecture, testing, Aktouf, C., Jan.-Feb. 02, pp. 18-28.

Coprocessors

Eclipse, heterogeneous, multiprocessor architecture, for flexible media, Rutten, M.J., et al., July-Aug. 02, pp. 39-50.

Cost-benefit analysis

IC testing, DFT economics, Nag, P.K., et al., Jan.-Feb. 02, pp. 29-41.

test economics, from the 2001 special ITC section, Jan.-Feb. 02, pp. 29-41.

Crosstalk

deep-submicron designs, substrate coupling, Silveira, L.M., et al., Mar.-Apr. 02, pp. 4-15.

very deep-submicron ICs, online testing approach, Favalli, M., et al., Mar.-Apr. 02, pp. 16-23.

Cyclic accelerators,
see Storage rings, Synchrotrons
Data acquisition

LHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.

Data conversion,
see Analog-digital conversion, Digital-analog conversion
Defect states

defect-oriented testing in the deep-submicron era, special issue, Sept.-Oct. 02, pp. 5-52.

defect-oriented testing in the deep-submicron era, guest editors' introduction, Segura, J., et al., Sept.-Oct. 02, pp. 5-7.

Delays

very deep-submicron ICs, online testing approach, Favalli, M., et al., Mar.-Apr. 02, pp. 16-23.

Design cost

cost of design, Kahng, A.B., The Road Ahead, Nov.-Dec. 02, pp. 136, 135.

Design engineering

leakage and process variation effects in current testing on future CMOS circuits, Keshavarzi, A., et al., Sept.-Oct. 02, pp. 36-43.

deep-submicron challenges, From the EIC, Gupta, R., Mar.-Apr. 02, p. 3.

design and test education in Latin America (LATW 2001 Roundtable), May-June 02, pp. 106-113.

design automation, special DAC section, July-Aug. 02, pp. 72-130.

design automation, guest editors' introduction, Blaauw, D., et al., July-Aug. 02, pp. 72-73.

disciplined approach to develop architectural platforms, Mihal, A., et al., Nov.-Dec. 02, pp. 6-16.

embedded systems, special issue, July-Aug. 02, pp. 5-69.

embedded systems, guest editor's introduction, Marwedel, P., July-Aug. 02, pp. 5-6.

high defect coverage with low-power test sequences in BIST environment, Girard, P., et al., Sept.-Oct. 02, pp. 44-52.

infrastructure IP for SoCs, special issue, May-June 02, pp. 5-70.

infrastructure IP for SoCs, guest editor's introduction, Zorian, Y., May-June 02, pp. 5-7.

ITC, special ITC section, Sept.-Oct. 02, pp. 54-91.

ITC, guest editors' introduction, Aitken, R., et al., Sept.-Oct. 02, pp. 54-55.

methodology for synthesis of data path circuits, Chowdhary, A., et al., Nov.-Dec. 02, pp. 90-100.

multiprocessor SoC platforms, component-based design approach, Cesário, W., et al., Nov.-Dec. 02, pp. 52-63.

test economics, from the 2001 special ITC section, Jan.-Feb. 02, pp. 29-41.

variability The Road Ahead, Kahng, A.B., May-June 02, pp. 120,116.

virtual simulation of distributed IP-based designs, Dalpasso, M., et al., Sept.-Oct. 02, pp. 92-104.

Design for testability

deep-submicron design and testing, special issue, Mar.-Apr. 02, pp. 3-58.

deep-submicron design and testing, From the EIC, Gupta, R., Mar.-Apr. 02, p. 3.

defect-oriented testing in the deep-submicron era, special issue, Sept.-Oct. 02, pp. 5-52.

defect-oriented testing in the deep-submicron era, guest editors' introduction, Segura, J., et al., Sept.-Oct. 02, pp. 5-7.

design automation, special DAC section, July-Aug. 02, pp. 72-130.

design automation, guest editors' introduction, Blaauw, D., et al., July-Aug. 02, pp. 72-73.

IC testing, DFT economics, Nag, P.K., et al., Jan.-Feb. 02, pp. 29-41.

LHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.

test economics, from the 2001 special ITC section, Jan.-Feb. 02, pp. 29-41.

Digital-analog conversion

mixed-signal, yield improvement strategy, Bordelon, J., et al., May-June 02, pp. 14-23.

Digital arithmetic,
see Coprocessors
Digital computers,
see Parallel machines
Digital filters,
see Median filters
Digital integrated circuits,
see Integrated logic circuits, Microprocessor chips
Digital signal processing chips

embedded tools for configurable and customizable DSP architecture, Liem, C., et al., Nov.-Dec. 02, pp. 27-35.

Digital simulation,
see Virtual machines
Digital storage,
see Random-access storage
Digital systems,
see Multiprocessing systems, Real-time systems
Direct energy conversion,
see Cells (electric)
Distributed processing

virtual simulation of distributed IP-based designs, Dalpasso, M., et al., Sept.-Oct., 02, pp. 92-104.

Distributed processing,
see Multiprocessing systems, Parallel processing
Economics,
see IC economics
Education

design and test education in Latin America (LATW 2001 Roundtable), May-June 02, pp. 106-113.

Electrical engineering computing,
see Automatic test software
Electrical faults,
see Fault location
Electric resistance measurement

resistance characterization for weak open defects, Rodríguez Montañés, R., et al., Sept.-Oct. 02, pp. 18-26.

Electric variables measurement,
see Voltage measurement
Electrochemical devices,
see Cells (electric)
Electron device manufacturing,
see IC manufacturing
Electronic design automation

CAD-IP reuse, Web bookshelf of fundamental algorithms, Caldwell, A.E., et al., May-June 02, pp. 72-81.

design automation, special DAC section, July-Aug. 02, pp. 72-130.

design automation, guest editors' introduction, Blaauw, D., et al., July-Aug. 02, pp. 72-73.

Verilog and other standards, Ashenden, P.J., Jan.-Feb. 02, pp. 84-85.

Electronic design automation,
see Circuit CAD
Electronic engineering,
see Low-power electronics
Electronic engineering computing,
see Electronic design automation, Logic CAD, Logic simulation
Electronic equipment testing,
see Circuit testing, Telecommunication equipment testing
Embedded systems

Eclipse, heterogeneous, multiprocessor architecture for flexible media, Rutten, M.J., et al., July-Aug. 02, pp. 39-50.

embedded systems, special issue, July-Aug. 02, pp. 5-69.

embedded systems, guest editor's introduction, Marwedel, P., July-Aug. 02, pp. 5-6.

embedded software-based self-test for programmable, core-based designs, Krstic, A., et al., July-Aug. 02, pp. 18-27.

embedded systs., design verification, multilevel testing, Schulz, S., et al., Mar.-Apr., 02, pp. 60-69.

embedded tools for configurable and customizable DSP architecture, Liem, C., et al., Nov.-Dec. 02, pp. 27-35.

FlexWare, retargetable embedded software development environment, Paulin, P.G., et al., July-Aug. 02, pp. 59-69.

infrastructure IP for SoCs, special issue, May-June 02, pp. 5-70.

infrastructure IP for SoCs, guest editor's introduction, Zorian, Y., May-June 02, pp. 5-7.

retargetable compiler design for embedded processors, Leupers, R., July-Aug. 02, pp. 51-58.

retargetable embedded in-circuit, emulation module for microprocessors, Huang, I.-J., et al., July-Aug. 02, pp. 28-38.

SES energy monitoring tool for low-power embedded programs, Shin, D., et al., July-Aug. 02, pp. 7-17.

Engineering,
see Design engineering
Engineering computing,
see Virtual machines
Estimation theory,
see Sequential estimation
Fault currents,
see Leakage currents
Fault diagnosis

bus-structured systems, interconnect fault, analysis/diagnosis, Zhao, J., et al., Jan.-Feb. 02, pp. 54-64.

scan-based BIST, rapid diagnosis, deterministic partitioning, Bayraktaroglu, I., et al., Jan.-Feb. 02, pp. 42-53.

Fault diagnosis,
see Fault location
Fault location

very deep-submicron ICs, online testing approach, Favalli, M., et al., Mar.-Apr. 02, pp. 16-23.

Field effect analog ICs,
see MOS analog ICs
Field programmable gate arrays

LHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.

Filters

practical oscillation-based test of integrated filters, Huertas, G., et al., Nov.-Dec., 02, pp. 64-72.

Formal specification

communication, controller hardware, automatic synthesis, Siegmund, R., et al., July-Aug. 02, pp. 84-95.

embedded systems, design verification, multilevel testing, Schulz, S., et al., Mar.-Apr., 02, pp. 60-69.

hardware designs, functional validation using formal specifications, Shimizu, K., et al., July-Aug. 02, pp. 96-106.

variability, The Road Ahead, Kahng, A.B., May-June 02, pp. 120,116.

Formal verification

embedded systems, design verification, multilevel testing, Schulz, S., et al., Mar.-Apr., 02, pp. 60-69.

hardware designs, functional validation using formal specifications, Shimizu, K., et al., July-Aug. 02, pp. 96-106.

Frequency synthesizers

fractional-N frequency, synthesizers, behavioral simulation, Perrott, M.H., July-Aug. 02, pp. 74-83.

Hardware description languages

fractional-N frequency, synthesizers, behavioral simulation, Perrott, M.H., July-Aug. 02, pp. 74-83.

Hardware-software codesign

hardware-software real-time operating system framework for SoCs, Mooney, V., et al., Nov.-Dec. 02, pp. 44-51.

embedded systems, design verification, multilevel testing, Schulz, S., et al., Mar.-Apr., 02, pp. 60-69.

High energy physics instrumentation computing

LHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.

High level synthesis,
see Hardware-software codesign
IEEE

constituting good standard, Standards, Ashenden, P.J., May-June 02, p. 114.

variability, The Road Ahead, Kahng, A.B., May-June 02, pp. 120,116.

IEEE standards

ETM10 incorporates hardware segment of IEEE P1500, McLaurin, T., et al., May-June 02, pp. 8-13.

IEEE standards process, Ashenden, P.J., Mar.-Apr. 02, pp. 72-73.

Verilog and other standards, Ashenden, P.J., Jan.-Feb. 02, pp. 84-85.

Image coding,
see Video coding
Image processing

deep-submicron challenges, From the EIC, Gupta, R., Mar.-Apr. 02, p. 3.

wafer defect cluster identification, image processing, Huang, C.-J., et al., Mar.-Apr. 02, pp. 44-48.

Industrial property

CAD-IP reuse, Web bookshelf of fundamental algorithms, Caldwell, A.E., et al., May-June 02, pp. 72-81.

embedded robustness IPs for transient-error-free ICs, Dupont, E., et al., May-June 02, pp. 56-70.

intellectual property for embedded diagnosis, Pateras, S., May-June 02, pp. 46-55.

Inspection,
see Automatic optical inspection
IC design

CMOS circuits, with subvolt supply voltages, Stan, M.R., Mar.-Apr. 02, pp. 34-43.

deep-submicron challenges, From the EIC, Gupta, R., Mar.-Apr. 02, p. 3.

deep-submicron designs, substrate coupling, Silveira, L.M., et al., Mar.-Apr. 02, pp. 4-15.

IC design,
see Integrated circuit layout
IC economics

IC testing, DFT economics, Nag, P.K., et al., Jan.-Feb. 02, pp. 29-41.

IC layout

MOS analog-design reuse, resizing rules and MOSFET model, Galup-Montoro, C., et al., Mar.-Apr. 02, pp. 50-58.

IC manufacturing

wafer defect cluster identification, image processing, Huang, C.-J., et al., Mar.-Apr. 02, pp. 44-48.

IC manufacturing,
see IC economics
IC modeling

MOS analog-design reuse, resizing rules and MOSFET model, Galup-Montoro, C., et al., Mar.-Apr. 02, pp. 50-58.

ICs

deep-submicron challenges, From the EIC, Gupta, R., Mar.-Apr. 02, p. 3.

ITC, special ITC section, Sept.-Oct. 02, pp. 54-91.

ITC, guest editors' introduction, Aitken, R., et al., Sept.-Oct. 02, pp. 54-55.

variability, The Road Ahead, Kahng, A.B., May-June 02, pp. 120,116.

IC testing

deep-submicron designs, substrate coupling, Silveira, L.M., et al., Mar.-Apr. 02, pp. 4-15.

deep-submicron IC, I DDQ testing, Chen, Z., et al., Mar.-Apr. 02, pp. 24-33.

DFT economics, Nag, P.K., et al., Jan.-Feb. 02, pp. 29-41.

embedded robustness IPs for transient-error-free ICs, Dupont, E., et al., May-June 02, pp. 56-70.

embedded software-based self-test for programmable, core-based designs, Krstic, A., et al., July-Aug. 02, pp. 18-27.

low-power VLSI circuit testing, Girard, P., May-June 02, pp. 82-92.

very deep-submicron ICs, online testing approach, Favalli, M., et al., Mar.-Apr. 02, pp. 16-23.

wafer defect cluster identification, image processing, Huang, C.-J., et al., Mar.-Apr. 02, pp. 44-48.

Integrated logic circuits

testing mixed-signal cores, practical oscillation-based test in analog macrocell, Huertas, G., et al., Nov.-Dec. 02, pp. 73-82.

Interconnections

bus-structured systems, interconnect fault, analysis/diagnosis, Zhao, J., et al., Jan.-Feb. 02, pp. 54-64.

Interference (signal),
see Crosstalk
Jitter

gigabit serial communication, transceivers, jitter testing, Yi Cai, et al., Jan.-Feb. 02, pp. 66-74.

SoC infrastructure, embedded timing analysis, Tabatabaei, S., et al., May-June 02, pp. 24-36.

Large-scale integration,
see VLSI
Leakage currents

deep-submicron IC, I DDQ testing, Chen, Z., et al., Mar.-Apr. 02, pp. 24-33.

Localized states,
see Defect states
Logic

efficient sequential test generation based on logic simulation, Sheng, S., et al., Sept.-Oct. 02, pp. 56-64.

Logic,
see Logic design, Logic simulation, Logic testing
Logic CAD

asynchronous circuits, synchronous CAD tools, Kondratyev, A., et al., July-Aug. 02, pp. 107-117.

Logic circuits,
see Asynchronous circuits, Integrated logic circuits
Logic design

design for debug, catching design errors in digital chips, Vermeulen, B., et al., May-June 02, pp. 37-45.

mixed-signal, yield improvement strategy, Bordelon, J., et al., May-June 02, pp. 14-23.

SoC infrastructure, embedded timing analysis, Tabatabaei, S., et al., May-June 02, pp. 24-36.

Logic design,
see Logic partitioning
Logic partitioning

scan-based BIST, rapid diagnosis, deterministic partitioning, Bayraktaroglu, I., et al., Jan.-Feb. 02, pp. 42-53.

Logic simulation

ITC, special ITC section, Sept.-Oct. 02, pp. 54-91.

ITC, guest editors' introduction, Aitken, R., et al., Sept.-Oct. 02, pp. 54-55.

scan-based BIST, rapid diagnosis, deterministic partitioning, Bayraktaroglu, I., et al., Jan.-Feb. 02, pp. 42-53.

Logic testing

design for debug, catching design errors in digital chips, Vermeulen, B., et al., May-June 02, pp. 37-45.

embedded robustness IPs for transient-error-free ICs, Dupont, E., et al., May-June 02, pp. 56-70.

embedded software-based self-test for programmable, core-based designs, Krstic, A., et al., July-Aug. 02, pp. 18-27.

ETM10 incorporates hardware segment of IEEE P1500, McLaurin, T., et al., May-June 02, pp. 8-13.

intellectual property for embedded diagnosis, Pateras, S., May-June 02, pp. 46-55.

mixed-signal, yield improvement strategy, Bordelon, J., et al., May-June 02, pp. 14-23.

scan-based BIST, rapid diagnosis, deterministic partitioning, Bayraktaroglu, I., et al., Jan.-Feb. 02, pp. 42-53.

SoC infrastructure, embedded timing analysis, Tabatabaei, S., et al., May-June 02, pp. 24-36.

very deep-submicron ICs, online testing approach, Favalli, M., et al., Mar.-Apr. 02, pp. 16-23.

Low-power electronics

battery-driven, system-level power management, Lahiri, K., et al., July-Aug. 02, pp. 118-130.

deep-submicron IC, I DDQ testing, Chen, Z., et al., Mar.-Apr. 02, pp. 24-33.

low-power VLSI circuit testing, Girard, P., May-June 02, pp. 82-92.

subvolt supply voltages, Stan, M.R., Mar.-Apr. 02, pp. 34-43.

Management,
see Cost-benefit analysis
Manufacturing

infrastructure IP for SoCs, special issue, May-June 02, pp. 5-70.

infrastructure IP for SoCs, guest editor's introduction, Zorian, Y., May-June 02, pp. 5-7.

variability, The Road Ahead, Kahng, A.B., May-June 02, pp. 120,116.

Mathematical analysis,
see Time-domain analysis
Measurement

variability, The Road Ahead, Kahng, A.B., May-June 02, pp. 120,116.

Median filters

wafer defect cluster identification, image processing, Huang, C.-J., et al., Mar.-Apr. 02, pp. 44-48.

Meetings

design and test education in Latin America, LATW 2001 Roundtable, May-June 02, pp. 106-113.

test economics, from the 2001 special ITC section, Jan.-Feb. 02, pp. 29-41.

Microprocessor chips

embedded systems, special issue, July-Aug. 02, pp. 5-69.

embedded systems, guest editor's introduction, Marwedel, P., July-Aug. 02, pp. 5-6.

embedded software-based self-test for programmable, core-based designs, Krstic, A., et al., July-Aug. 02, pp. 18-27.

multiprocessor SoC platforms, component-based design approach, Cesário, W., et al., Nov.-Dec. 02, pp. 52-63.

retargetable embedded in-circuit, emulation module for microprocessors, Huang, I.-J., et al., July-Aug. 02, pp. 28-38.

Microprocessor chips,
see Coprocessors, Digital signal processing chips
MISFET,
see MOSFET
Mixed analog-digital ICs

deep-submicron designs, substrate coupling, Silveira, L.M., et al., Mar.-Apr. 02, pp. 4-15.

mixed-sig, yield improvement strategy, Bordelon, J., et al., May-June 02, pp. 14-23.

Modeling

test economics, from the 2001 special ITC section, Jan.-Feb. 02, pp. 29-41.

Modeling,
see IC modeling, Semiconductor device models
Modules,
see Multichip modules
Monolithic ICs,
see Application-specific ICs
MOS analog ICs

resizing rules for MOS analog-design reuse, Galup-Montoro, C., et al., Mar.-Apr. 02, pp. 50-58.

MOSFET

resizing rules and MOSFET model for MOS analog-design reuse, Galup-Montoro, C., et al., Mar.-Apr. 02, pp. 50-58.

MOS ICs,
see CMOS ICs, MOS analog ICs
Multichip modules

LHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.

significance of packaging, Kahng, A.B., The Road Ahead, Nov.-Dec. 02, pp. 104-105.

Multiprocessing systems

Eclipse, heterogeneous multiprocessor architecture for flexible media, Rutten, M.J., et al., July-Aug. 02, pp. 39-50.

large-area, integrated multiprocessor system for video coding, Rudack, M., et al., Jan.-Feb. 02, pp. 6-17.

on-chip multiprocessor architecture, testing, Aktouf, C., Jan.-Feb. 02, pp. 18-28.

Multiprocessor interconnection networks

application-specific SoC multiprocessors, special issue, Jan.-Feb. 02, pp. 6-28.

Network routing

on-chip multiprocessor architecture, testing, Aktouf, C., Jan.-Feb. 02, pp. 18-28.

Networks (circuits)

infrastructure IP for SoCs, special issue, May-June 02, pp. 5-70.

infrastructure IP for SoCs, guest editor's introduction, Zorian, Y., May-June 02, pp. 5-7.

methodology for synthesis of data path circuits, Chowdhary, A., et al., Nov.-Dec. 02, pp. 90-100.

Networks (circuits),
see Analog circuits, Coupled circuits, Filters, Integrated circuits, Oscillators, Phase-locked loops
Network synthesis

SoC, reproducible design flow, Magarshack, P., Jan.-Feb. 02, pp. 76-83.

Network synthesis,
see Circuit CAD, IC design
Network topology

application-specific SoC multiprocessors, special issue, Jan.-Feb. 02, pp. 6-28.

Noise generators

noise generation and coupling mechanisms in deep-submicron ICs, Aragonès, X., et al., Sept.-Oct. 02, pp. 27-35.

Nuclear electronics

LHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.

Operating systems (computers)

hardware-software real-time operating system framework for SoCs, Mooney, V., et al., Nov.-Dec. 02, pp. 44-51.

Optimizing compilers

retargetable compiler design for embedded processors, Leupers, R., July-Aug. 02, pp. 51-58.

Oscillations

practical oscillation-based test of integrated filters, Huertas, G., et al., Nov.-Dec., 02, pp. 64-72.

Oscillators

testing mixed-signal cores, practical oscillation-based test in analog macrocell, Huertas, G., et al., Nov.-Dec. 02, pp. 73-82.

Packaging,
see Multichip modules
Parallel architectures

on-chip multiprocessor architecture, testing, Aktouf, C., Jan.-Feb. 02, pp. 18-28.

Parallel machines

on-chip multiprocessor architecture, testing, Aktouf, C., Jan.-Feb. 02, pp. 18-28.

Parallel processing

application-specific SoC multiprocessors, special issue, Jan.-Feb. 02, pp. 6-28.

Parallel processing,
see Parallel architectures, Parallel machines
Particle accelerators,
see Colliding beam accelerators
Particle calorimetry

LHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.

Performance evaluation

improving defect detection in static-voltage testing, Renovell, M., et al., Nov.-Dec. 02, pp. 83-89.

variability, The Road Ahead, Kahng, A.B., May-June 02, pp. 120,116.

Performance evaluation,
see Software performance evaluation
Phase locked loops

fractional-N frequency, synthesizers, behavioral simulation, Perrott, M.H., July-Aug. 02, pp. 74-83.

Physics computing,
see High-energy physics instrumentation computing
Platform-based design

Platform-based design of SoCs, special issue, Nov.-Dec. 02, pp. 4-63.

Platform-based design of SoCs, guest editor's introduction, Nov.-Dec. 02, pp. 4-5.

Power consumption

battery-driven, system-level power management, Lahiri, K., et al., July-Aug. 02, pp. 118-130.

Program compilers

embedded systems, special issue, July-Aug. 02, pp. 5-69.

embedded processors, guest editor's introduction, Marwedel, P., July-Aug. 02, pp. 5-6.

embedded tools for configurable and customizable DSP architecture, Liem, C., et al., Nov.-Dec. 02, pp. 27-35.

Program compilers,
see Optimizing compilers
Program debugging

intellectual property for embedded diagnosis, Pateras, S., May-June 02, pp. 46-55.

Program diagnostics

infrastructure IP for SoCs, special issue, May-June 02, pp. 5-70.

infrastructure IP for SoCs, guest editor's introduction, Zorian, Y., May-June 02, pp. 5-7.

Programmable logic arrays,
see Field-programmable gate arrays
Programming,
see Program testing, Software tools
Program processors

StepNP, system-level exploration platform for network processors, Paulin, P., et al., Nov.-Dec. 02, pp. 17-26.

Program processors,
see Program compilers
Program testing

embedded systems, design verification, multilevel testing, Schulz, S., et al., Mar.-Apr., 02, pp. 60-69.

Protocols

communication, controller hardware, automatic synthesis, Siegmund, R., et al., July-Aug. 02, pp. 84-95.

Radiation detection,
see Particle calorimetry
Radio equipment,
see Transceivers
Random-access storage

on-chip multiprocessor architecture, testing, Aktouf, C., Jan.-Feb. 02, pp. 18-28.

Readout electronics

LHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.

Real-time systems

hardware-software real-time operating system framework for SoCs, Mooney, V., et al., Nov.-Dec. 02, pp. 44-51.

intellectual property for embedded diagnosis, Pateras, S., May-June 02, pp. 46-55.

large-area, integrated multiprocessor system for video coding, Rudack, M., et al., Jan.-Feb. 02, pp. 6-17.

Real-time systems,
see Embedded systems
Reconfigurable architectures

Eclipse, heterogeneous multiprocessor architecture for flexible media, Rutten, M.J., et al., July-Aug. 02, pp. 39-50.

Redundancy

large-area, integrated multiprocessor system for video coding, Rudack, M., et al., Jan.-Feb. 02, pp. 6-17.

Reliability

infrastructure IP for SoCs, special issue, May-June 02, pp. 5-70.

infrastructure IP for SoCs, guest editor's introduction, Zorian, Y., May-June 02, pp. 5-7.

Satellite computers,
see Coprocessors
Semiconductor counters,
see Silicon radiation detectors
Semiconductor device models

MOS analog-design reuse, resizing rules and MOSFET model, Galup-Montoro, C., et al., Mar.-Apr. 02, pp. 50-58.

Sequential estimation

efficient sequential test generation based on logic simulation, Sheng, S., et al., Sept.-Oct. 02, pp. 56-64.

Signal generators,
see Frequency synthesizers, Noise generators
Signal processing,
see Digital signal processing chips, Image processing
Silicon radiation detectors

LHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.

Simulation

efficient sequential test generation based on logic simulation, Sheng, S., et al., Sept.-Oct. 02, pp. 56-64.

virtual simulation of distributed IP-based designs, Dalpasso, M., et al., Sept.-Oct. 02, pp. 92-104.

Simulation,
see Circuit simulation, Logic simulation
Smoothing methods,
see Median filters
Software engineering,
see Formal specification, Formal verification, Software performance evaluation, Software reusability, Software tools
Software performance evaluation

SES energy monitoring tool for low-power embedded programs, Shin, D., et al., July-Aug. 02, pp. 7-17.

Software reusability

CAD-IP reuse, Web bookshelf of fundamental algorithms, Caldwell, A.E., et al., May-June 02, pp. 72-81.

Software tools

FlexWare, retargetable embedded software development environment, Paulin, P.G., et al., July-Aug. 02, pp. 59-69.

SES energy monitoring tool for low-power embedded programs, Shin, D., et al., July-Aug. 02, pp. 7-17.

Special issues and sections

application-specific SoC multiprocessors, special issue, Jan.-Feb. 02, pp. 6-28.

defect-oriented testing in the deep-submicron era, special issue, Sept.-Oct. 02, pp. 5-52.

design automation, special DAC section, July-Aug. 02, pp. 72-130.

embedded systems, special issue, July-Aug. 02, pp. 5-69.

infrastructure IP for SoCs, special issue, May-June 02, pp. 5-70.

ITC, special ITC section, Sept.-Oct. 02, pp. 54-91.

test economics, from the 2001 special ITC section, Jan.-Feb. 02, pp. 29-41.

Specification languages,
see Hardware description languages
Standards

constituting good standard, Standards, Ashenden, P.J., May-June 02, p. 114.

variability, The Road Ahead, Kahng, A.B., May-June 02, pp. 120,116.

Standards,
see IEEE standards
Storage rings

LHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.

Substrates

deep-submicron designs, substrate coupling, Silveira, L.M., et al., Mar.-Apr. 02, pp. 4-15.

Switching networks,
see Multiprocessor interconnection networks
Synchrotrons

LHC high-energy physics experiments, MCM array, DFT and BIST, Benso, A., et al., May-June 02, pp. 94-105.

System buses

interconnect fault, analysis/diagnosis, Zhao, J., et al., Jan.-Feb. 02, pp. 54-64.

System monitoring

improving defect detection in static-voltage testing, Renovell, M., et al., Nov.-Dec. 02, pp. 83-89.

System monitoring,
see Program diagnostics
Systems analysis

infrastructure IP for SoCs, special issue, May-June 02, pp. 5-70.

infrastructure IP for SoCs, guest editor's introduction, Zorian, Y., May-June 02, pp. 5-7.

Systems software,
see Operating systems (computers), Program processors, System monitoring
Telecommunication equipment testing

gigabit serial communication, transceivers, jitter testing, Cai, Y., et al., Jan.-Feb. 02, pp. 66-74.

Testing

deep-submicron challenges, From the EIC, Gupta, R., Mar.-Apr. 02, p. 3.

defect-oriented testing in the deep-submicron era, special issue, Sept.-Oct. 02, pp. 5-52.

defect-oriented testing in the deep-submicron era, guest editors' introduction, Segura, J., et al., Sept.-Oct. 02, pp. 5-7.

design and test education in Latin America (LATW 2001 Roundtable), May-June 02, pp. 106-113.

design automation, special DAC section, July-Aug. 02, pp. 72-130.

design automation, guest editors' introduction, Blaauw, D., et al., July-Aug. 02, pp. 72-73.

efficient sequential test generation based on logic simulation, Sheng, S., et al., Sept.-Oct. 02, pp. 56-64.

embedded systems, special issue, July-Aug. 02, pp. 5-69.

embedded systems, guest editor's introduction, Marwedel, P., July-Aug. 02, pp. 5-6.

extending OPMISR beyond 10x scan test efficiency, Barnhart, C., et al., Sept.-Oct. 02, pp. 65-73.

high defect coverage with low-power test sequences in BIST environment, Girard, P., et al., Sept.-Oct. 02, pp. 44-52.

I DDQ test, surviving the DSM challenge, Sabade, S, et al., Sept.-Oct. 02, pp. 8-16.

infrastructure IP for SoCs, special issue, May-June 02, pp. 5-70.

infrastructure IP for SoCs, guest editor's introduction, Zorian, Y., May-June 02, pp. 5-7.

leakage and process variation effects in current testing on future CMOS circuits, Keshavarzi, A., et al., Sept.-Oct., 02, pp. 36-43.

multilevel testability analysis and solutions for integrated Bluetooth transceivers, Ozev, S., et al., Sept.-Oct. 02, pp. 82-91.

neighborhood selection for I DDQ outlier screening at wafer sort, Daasch, W, et al., Sept.-Oct. 02, pp. 74-81.

practical oscillation-based test of integrated filters, Huertas, G., et al., Nov.-Dec., 02, pp. 64-72.

testing mixed-signal cores, practical oscillation-based test in analog macrocell, Huertas, G., et al., Nov.-Dec. 02, pp. 73-82.

Testing,
see Automatic testing, Boundary scan testing, Built-in self test, Computer testing, Logic testing, Program testing
Time-domain analysis

SoC infrastructure, embedded timing analysis, Tabatabaei, S., et al., May-June 02, pp. 24-36.

Timing

very deep-submicron ICs, online testing approach, Favalli, M., et al., Mar.-Apr. 02, pp. 16-23.

Topology,
see Network topology
Transceivers

gigabit serial communication transceivers, jitter testing, Yi Cai, et al., Jan.-Feb. 02, pp. 66-74.

multilevel testability analysis and solutions for integrated Bluetooth transceivers, Ozev, S., et al., Sept.-Oct. 02, pp. 82-91.

Video coding

application-specific SoC multiprocessors, special issue, Jan.-Feb. 02, pp. 6-28.

large-area, integrated multiprocessor system for video coding, Rudack, M., et al., Jan.-Feb. 02, pp. 6-17.

Video signal processing,
see Video coding
Virtual machines

hardware designs, functional validation using formal specifications, Shimizu, K., et al., July-Aug. 02, pp. 96-106.

VLSI

CAD-IP reuse, Web bookshelf of fundamental algorithms, Caldwell, A.E., et al., May-June 02, pp. 72-81.

low-power VLSI circuit, testing, Girard, P., May-June 02, pp. 82-92.

very deep-submicron ICs, online testing approach, Favalli, M., et al., Mar.-Apr. 02, pp. 16-23.

VLSI,
see Wafer-scale integration
Voltage measurement

improving defect detection in static-voltage testing, Renovell, M., et al., Nov.-Dec. 02, pp. 83-89.

Wafer-scale integration

deep-submicron challenges, From the EIC, Gupta, R., Mar.-Apr. 02, p. 3.

wafer defect cluster identification, image processing, Huang, C.-J., et al., Mar.-Apr. 02, pp. 44-48.

 
 
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