Digitally Enhanced Wireless Transceivers
Final submissions due: 1 March 2012
Publication date: November/December 2012
Current and next-generation electronic systems and devices increasingly rely on wireless communication. The massive and relatively inexpensive (in terms of silicon area) digital processing resources available in modern technologies open new opportunities for digitally intensive wireless system design. The replacement of the analog, mixed-signal, and RF functions by entirely digital or digitally assisted components is a recent trend to improve the performance of wireless systems, as well as to reduce their power dissipation and form factor. In addition, communication functions based on digital building blocks open opportunities for new radio and subsystem architectures.
As the performance expectations for wireless communication systems grow and their applications become pervasive, their testing becomes more challenging and complex. The digitally assisted design paradigm offers improved testability since it can make use of mature digital-test solutions. It can accommodate the implementation of smart built-in self-test solutions to increase parallelism (test throughput), reduce the dependence on expensive test infrastructure by providing digital test signatures, diagnose failures at the block level, and provide valuable feedback for yield enhancement. Digitally assisted designs can also facilitate the on-chip implementation of automatic calibration procedures as part of the test procedure to correct for yield loss after fabrication. Test-calibration loops can be designed in the test mode to re-center the design to the desired specifications.
IEEE Design & Test seeks original manuscripts for this special issue scheduled for publication in November/December 2012.
The topics of interest include (but are not limited to) the following:
- Design of all-digital and digitally assisted transceiver components
- Digitally enhanced transceiver architectures
- On-chip calibration of RF circuits
- Digitally driven design-for-test and built-in self-test techniques for transceivers
Submission and review procedures
Prospective authors should follow the submission guidelines for IEEE Design & Test. All manuscripts must be submitted electronically to the IEEE Manuscript Central Web site at https://mc.manuscriptcentral.com/cs-ieee. Indicate that you are submitting your article to the special issue on “Digitally Enhanced Wireless Transceivers.” All articles will undergo the standard IEEE Design & Test review process. Submitted manuscripts must not have been previously published or currently submitted for publication elsewhere. Manuscripts must not exceed 5,000 words, including figures (with each average-size figure counting as 200 words) and a maximum of 12 References (30 for surveys). This amounts to about 4,000 words of text and a maximum of five small to medium figures. Accepted articles will be edited for clarity, structure, conciseness, grammar, logical organization, readability, and adherence to D&T and Computer Society style. Please see IEEE D&T Author Resources at http://www.computer.org/dt/author.htm, then scroll down and click on Author Center for submission guidelines and requirements.
Schedule
- Submissions due: 1 March 2012
- Reviews completed: 1 June 2012
- Revisions due (if needed): 1 July 2012
- Notice of final acceptance: 1 August 2012
- All materials due for edit: 15 September 2012
- Publication date: November/December 2012
Questions?
Please direct questions regarding this special issue to Guest Editors Haralampos-G. Stratigopoulos and Alberto Valdes-Garcia.