NOVEL ARCHITECTURES


Computing in Science & Engineering, May/June 2009, pp. 54–57

illustration of futuristic architecture 

Novel Computing Architectures

by Volodymyr V. Kindratenko

For a while, microprocessor frequency increased for each successive reduction in semiconductor feature size, but recently this increase came to a complete stop as the semiconductor industry struggled with increased power density. In fact, since 2002, microprocessor frequency has largely remained flat, whereas semiconductor transistor size still continues to decrease in accordance with Moore’s law, which postulates that as semiconductor feature size shrinks with each successive generation, the number of transistors on a chip doubles approximately every two years.

The semiconductor industry has turned its attention to new chip architectures that can still take advantage of shrinking transistor size, rather than fight the “power wall”—an observation that as chips shrink and clock frequencies increase, the transistor leakage current increases, leading to excess power consumption and heat that, at some point, can’t be dealt with using existing cooling methods. Homogeneous multicore chips are the simplest of these new architectures in which chip manufacturers place multiple copies of the same microprocessor design on the same silicon die. The more complex chip designs involve processor cores with different functionality and capabilities integrated together to form system-on-chip (SoC) architectures that are typically made for specific application domains. This, in turn, has spawned an explosion in innovative computing system architectures ranging from using many-core graphics processing units (GPUs) to designing application specific machines using reconfigurable logic chips, such as field-programmable gate arrays (FPGAs).

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