Krishnendu Chakrabarty

Professor of Electrical and Computer Engineering
Duke University
129 Hudson Hall, Box 90291
Durham, NC 27708
Phone: +1 919 660 5244
E-mail: krish@ee.duke.edu
URL: www.ee.duke.edu/~krish


DVP term expires December 2012

Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of
Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of
Michigan, Ann Arbor, in 1992 and 1995, respectively, all in Computer Science and
Engineering. He is now Professor of Electrical and Computer Engineering at Duke
University.

Prof. Chakrabarty is a Fellow of IEEE, a Senior Member of ACM, and a Member of Sigma
Xi. He received a Meritorious Service Award from the IEEE Computer Society in 2008. Prof.
Chakrabarty is a recipient of Duke University's 2008 Dean's Award for Excellence in
Mentoring. He is also a recipient of the National Science Foundation Early Faculty
(CAREER) award (1999) and the Office of Naval Research Young Investigator award (2001).
His current research projects include: testing and design-for-testability of system-on-chip
integrated circuits; digital microfluidic biochips; nanotechnology circuits and systems based
on DNA self-assembly; delay-tolerant wireless networks.

Prof. Chakrabarty served as a Distinguished Visitor of the IEEE Computer Society for 2005-
2007 and as a Distinguished Lecturer of the IEEE Circuits and Systems Society for 2006-
2007. Since 2008, he is serving as an ACM Distinguished Speaker. He is an Associate Editor
of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE
Transactions on VLSI Systems, IEEE Transactions on Biomedical Circuits and Systems, and
ACM Journal on Emerging Technologies in Computing Systems, and an Editor of IEEE
Design & Test of Computers, and Journal of Electronic Testing: Theory and Applications
(JETTA). He recently completed his term as Associate Editor of IEEE Transactions on
Circuits and System I (2006-2007). He served as Program Chair for the 2005 IEEE Asian Test
Symposium and is the designed General Co-Chair for the 2010 IEEE Asian Test Symposium.
The nominee’s CV is available on the web at:
http://www.ee.duke.edu/~krish/CV.pdf

Automated Design of Digital Microfluidic Lab-on-Chip: Connecting Biochemistry to
Information Technology and Electronic Design Automation

Microfluidics-based lab-on-chip (or biochips) are revolutionizing laboratory procedures in
molecular biology, and leading to a convergence of information technology with biochemistry
and microelectronics. Advances in microfluidics technology offer exciting possibilities for
high-throughput DNA sequencing, protein crystallization, drug discovery, immunoassays,
neo-natal and point-of-care clinical diagnostics, etc. As microfluidic lab-on-chip mature into
multifunctional devices with "smart" reconfiguration and adaptation capabilities, automated
design and ease of use become extremely important.

This talk will present design automation and testing methods for droplet-based “digital”
microfluidic lab-on-chip. The speaker will first describe emerging applications in biology and
biochemistry that can benefit from advances in electronic “biochips”. The presenter will next
discuss technology platforms for accomplishing “biochemistry on a chip”, focusing especially
on the electrowetting-based digital microfluidic platform. Synthesis algorithms and methods
will be presented to map behavioral descriptions (e.g., laboratory protocols) to a digital
microfluidic platform, and generate an optimized schedule of bioassay operations, chip
layout, and droplet-flow paths. In this way, the audience will see how a “biochip compiler”
can translate protocol descriptions provided by an end user (e.g., a chemist or a nurse at a
doctor’s clinic) to a set of optimized and executable fluidic instructions that will run on the
underlying digital microfluidic platform. Testing techniques will be described to detect faults after manufacture and during field operation. A classification of defects will be presented based on data for fabricated chips. Appropriately fault models will be developed and presented to the audience. On-line and offline reconfiguration techniques will be presented to bypass faults once they are detected. The problem of mapping a small number of chip pins to a large number of array electrodes will also be covered. A number of case studies based on representative assays and laboratory procedures will be interspersed in appropriate places throughout the talk.

Advanced Test Techniques for Screening Unmodeled and Small-Delay Defects in
Very-Deep Submicron Integrated Circuits

Timing-related and unmodeled defects are major contributors to test escapes and in-field
reliability problems for very-deep submicron integrated circuits. Small delay variations
induced by crosstalk, process variations, power-supply noise, as well as resistive opens and
shorts can potentially cause timing failures in a design, thereby leading to quality and
reliability concerns. The complexity of today’s integrated circuits and shrinking process
technologies are also leading to prohibitively high test data volumes. As a result, the 2007
ITRS document predicts that the test data volume for integrated circuits will be as much as 38
times larger and the test application time will be about 17 times larger in 2015 than today.
The speaker will present emerging test techniques for defect screening, which uses the
method of output deviations for handling unmodeled faults. A new gate-delay defect
probability measure will be defined to model delay variations and erroneous behavior for
nanometer technologies. This approach requires significantly lower computational complexity
and lower pattern counts (thereby less test data volume and test time), and it excites a larger
number of long paths compared to commercial timing-aware test-generation tools. The
speaker will present results for benchmark and industrial circuits to highlight that show that,
with lower pattern count, the proposed method provides more effective coverage ramp-up
than timing-aware test generation. Finally, the speaker will describe the latest test-data
compression methods that use the output deviations measure for high-quality defect screening
at low cost.