Yale N. Patt

1996 Eckert-Mauchly Award Recipient
________________________________________________




“For important contributions to instruction level parallelism and superscalar processor design”


 

Yale Patt is Professor of Electrical and Computer Engineering and the Ernest Cockrell, Jr. Centennial Chair in Engineering at The University of Texas at Austin.

He enjoys equally teaching freshmen, teaching graduate students, and directing the research of nine PhD students in high performance computer implementation. He has, for more than 30 years, combined an active research program with extensive consulting and a strong commitment to teaching.

The focus of his research is generally five to ten years beyond what industry provides at that point in time. His rationale has always been that he does not do revenue shipments, preferring to produce knowledge that will be useful to future revenue shipments and, more importantly, graduates who will design those future products.

In 1965, Yale Patt introduced the WOS module, the first complex logic gate implemented on a single piece of silicon ["A complex logic module for the synthesis of combinatorial switching circuits," Proceedings of the 1967 Spring Joint Computer Conference, Atlantic City, April, 1967]. In 1984, he (and his students Wen-mei Hwu, Steve Melvin, and Mike Shebanow) introduced HPS, a high performance microarchitecture that exploits instruction level parallelism by combining wide-issue (fetching and issuing multiple instructions each cycle), aggressive dynamic branch prediction, dynamic scheduling, out-of-order execution, and checkpoint in-order retirement (enabling precise exceptions). The first two papers describing this work, "HPS, A New Microarchitecture: Rationale and Introduction" and "Critical Issues Regarding HPS, A High Performance Microarchitecture," were presented at Micro-18, and published in the Proceedings of the 18th Microprogramming Workshop, Asilomar, CA, December, 1985. In 1991 he (and his student Tse-Yu Yeh) introduced the Two-Level Branch Predictor, which provided much greater accuracy than was available before that. The paper, "Two-Level Adaptive Branch Prediction," was presented at Micro-24, and published in the Proceedings of the 24th International Symposium and workshop on Microarchitecture, Albuquerque, November, 1991.

Today, Yale Patt works on problems for the microprocessors of the year 2015, when technology promises each chip will contain more than ten billion transistors. Some of his current activities include Subordinate Simultaneous Microthreading (aka helper threads), a variation of Simultaneous Multithreading that is particularly useful in sequential threads of control, cluster processing, the Block-structured ISA, Selective V-way caches, Run-ahead execution, and Wish branches.

Much as he enjoys research, Professor Patt's first love is teaching. The focus of his teaching has always been on understanding the fundamentals. At Michigan, he overhauled the introductory computer organization course, the intensive computer design course, and (with his former colleague Kevin Compton) the first required computing course for undergraduate EE, CS, and CE majors. Their motivated bottom-up approach is the subject of the textbook, "Introduction to Computing Systems, From Bits and Gates to C and Beyond," McGraw-Hill, 2001, ISBN: 0-07-237690-2, which he co-authored with his former PhD student Sanjay Patel, who is now a tenured Associate Professor at the University of Illinois, Urbana-Champaign. The 2nd edition was published in 2004, ISBN 0-07-246750-9.

He has also taught more than 5000 engineers in industry, -- in ACM/IEEE conference tutorials and in short courses at company sites.

Yale Patt earned his BS at Northeastern University and his MS and PhD at Stanford University, all in electrical engineering. He received the 1995 IEEE Emannuel R. Piore Medal "for contributions to computer architecture leading to commercially viable high performance microprocessors," the 1996 IEEE/ACM Eckert-Mauchly Award "for important contributions to instruction level paralelism and superscalar processor design," and the 1999 IEEE Wallace W. McDowell Award "for your impact on the high performance microprocessor industry via a combination of important contributions to both engineering and education." In 2005, he received the IEEE Computer Society Charles Babbage Award "for fundamental contributions to high performance processor design." He is a Fellow of both the IEEE and the ACM.

For his teaching, he has received several awards, most notably the ACM Karl V. Karlstrom Outstanding Educator Award for 2000. He also received the 2002 Texas Excellence Teaching Award for the College of Engineering at The University of Texas at Austin. Also, the 2002 Dad's Centennial Fellowship for his commitment to teaching freshmen. At Michigan, he was named Outstanding Professor of the Year by the Michigan Chapter of Eta Kappa Nu in 1992. He received the Teaching Excellence Award of the EECS Department at Michigan in 1995 and the College of Engineering of Michigan in 1996. In 1998, he was named an Arthur F. Thurnau professor at Michigan for his commitment to undergraduate education. In 1999 (for the academic year 1998-1999), and again in 2001 (for the academic year 2000-2001), he was named the National ACM Lectureship Program's Outstanding Lecturer of the Year.