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UKSim 2009: 11th International Conference on Computer Modelling and Simulation
Design and Implementation of a 64-bit RISC Processor Using VHDL
March 25-March 27
ISBN: 978-0-7695-3593-7
In the present paper, we present the designand implementation of a 64-bit reduced instruction set(RISC) processor with built-in-self test (BIST) features. Abuilt-in self-test (BIST) or built-in test (BIT) is amechanism that permits a machine to test itself. Keyfeatures of the design including its architecture, datapath, and instruction set are presented. The design isimplemented using VHDL and verified on Xilinx ISEsimulator. The processor is designed keeping in mindspecific applications. The proposed design may findapplications where automation and control is required.Illustrations highlight the typical use of our processor inbottling plants and control of robotic movements usingexhaustive simulations. Future applications may includeits use in vending machines, ATMs, mobile phones, andportable gaming kits.
Index Terms:
RISC, BIST, BIT, VHDL
Citation:
Rohit Sharma, Vivek Kumar Sehgal, Nitin Nitin, Pranav Bhasker, Ishita Verma, "Design and Implementation of a 64-bit RISC Processor Using VHDL," uksim, pp.568-573, UKSim 2009: 11th International Conference on Computer Modelling and Simulation, 2009
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