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Sixth International Conference on Computational Intelligence and Multimedia Applications (ICCIMA'05)
A GA-Based Timing-Driven Placement Technique
Las Vegas, Nevada
August 16-August 18
ISBN: 0-7695-2358-7
| ASCII Text | x | ||
| Masaya Yoshikawa, Hidekazu Terai, "A GA-Based Timing-Driven Placement Technique," Computational Intelligence and Multimedia Applications, International Conference on, pp. 74-79, Sixth International Conference on Computational Intelligence and Multimedia Applications (ICCIMA'05), 2005. | |||
| BibTex | x | ||
| @article{ 10.1109/ICCIMA.2005.3, author = {Masaya Yoshikawa and Hidekazu Terai}, title = {A GA-Based Timing-Driven Placement Technique}, journal ={Computational Intelligence and Multimedia Applications, International Conference on}, volume = {0}, year = {2005}, isbn = {0-7695-2358-7}, pages = {74-79}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICCIMA.2005.3}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Computational Intelligence and Multimedia Applications, International Conference on TI - A GA-Based Timing-Driven Placement Technique SN - 0-7695-2358-7 SP74 EP79 A1 - Masaya Yoshikawa, A1 - Hidekazu Terai, PY - 2005 KW - null VL - 0 JA - Computational Intelligence and Multimedia Applications, International Conference on ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCIMA.2005.3
Deep-Sub-Micron technology (DSM) of 0.18 micron and below enable the integration of logical circuits having more than 10 million gates. In such a DSM technology, timing constraint has become the dominant factor in the performance of VLSI. This paper discusses a novel timing driven placement technique through Genetic Algorithm. The proposed algorithm has a two-level hierarchical structure consisting of outline placement and detail placement. For selection control, new objective functions are introduced for improving interconnect delay, power consumption and chip area. Experimental result shows improvement of 5.8 % for interconnect delay, 0.1% for power consumption and 0.8% for chip area.
Citation:
Masaya Yoshikawa, Hidekazu Terai, "A GA-Based Timing-Driven Placement Technique," iccima, pp.74-79, Sixth International Conference on Computational Intelligence and Multimedia Applications (ICCIMA'05), 2005
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