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Rapid Embedded System Testing Using Verification Patterns
July/August 2005 (vol. 22 no. 4)
pp. 68-75
Wei-Tek Tsai, Arizona State University
Lian Yu, Arizona State University
Feng Zhu, University of Minnesota
Ray Paul, US Department of Defense
The verification pattern (VP) approach for rapidly testing real-time embedded systems first classifies system scenarios into patterns. For each scenario pattern (SP), the approach develops a test script template to test all the scenarios belonging to that pattern. In this way, instead of developing numerous test scripts to test the system, test engineers can customize and reuse a set of test script templates to test the entire application, saving significant effort and time. This approach works particularly well for testing systems undergoing constant updates because test engineers can easily update or regenerate test scripts by reusing the test templates. The authors have applied this approach at industrial sites to test several safety-critical implantable medical devices. The applications significantly reduced cost and effort while maintaining the original quality requirements compared to the existing approaches.
Index Terms:
Software engineering, embedded systems testing, testing and debugging, testing tools, rapid testing, verification patterns, scenario patterns
Citation:
Wei-Tek Tsai, Lian Yu, Feng Zhu, Ray Paul, "Rapid Embedded System Testing Using Verification Patterns," IEEE Software, vol. 22, no. 4, pp. 68-75, July-Aug. 2005, doi:10.1109/MS.2005.103
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