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Formal Verification of a Pipelined Microprocessor
September/October 1990 (vol. 7 no. 5)
pp. 52-64
| ASCII Text | x | ||
| Mandayam Srivas, Mark Bickford, "Formal Verification of a Pipelined Microprocessor," IEEE Software, vol. 7, no. 5, pp. 52-64, September/October, 1990. | |||
| BibTex | x | ||
| @article{ 10.1109/52.57892, author = {Mandayam Srivas and Mark Bickford}, title = {Formal Verification of a Pipelined Microprocessor}, journal ={IEEE Software}, volume = {7}, number = {5}, issn = {0740-7459}, year = {1990}, pages = {52-64}, doi = {http://doi.ieeecomputersociety.org/10.1109/52.57892}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Software TI - Formal Verification of a Pipelined Microprocessor IS - 5 SN - 0740-7459 SP52 EP64 EPD - 52-64 A1 - Mandayam Srivas, A1 - Mark Bickford, PY - 1990 KW - pipelined microprocessor; modern functional languages; verification technology; infinite stream; machine instructions; interrupt signals; hardware design; correctness criterion; mechanically supported induction argument; functional-language-based verification system Clio; Mini Cayuga microprocessor; formal specification; verification process; functional programming; microprocessor chips; parallel architectures; parallel machines; program verification VL - 7 JA - IEEE Software ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/52.57892
The application of modern functional languages and supporting verification technology to a scaled-down but realistic microprocessor is described. The model is of an infinite stream of machine instructions consuming an infinite stream of interrupt signals and is specified at two levels: instruction and hardware design. A correctness criterion is stated for an appropriate sense of equivalent behavior of these levels and proved using a mechanically supported induction argument. The functional-language-based verification system Clio and the Mini Cayuga microprocessor are described. The formal specification and verification process are examined in detail.
Index Terms:
pipelined microprocessor; modern functional languages; verification technology; infinite stream; machine instructions; interrupt signals; hardware design; correctness criterion; mechanically supported induction argument; functional-language-based verification system Clio; Mini Cayuga microprocessor; formal specification; verification process; functional programming; microprocessor chips; parallel architectures; parallel machines; program verification
Citation:
Mandayam Srivas, Mark Bickford, "Formal Verification of a Pipelined Microprocessor," IEEE Software, vol. 7, no. 5, pp. 52-64, Sept.-Oct. 1990, doi:10.1109/52.57892
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