CSDL - IEEE Design and Test of Computers

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XML-Based Hierarchical Description of 3D Systems and SIP (PDF)

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Advances in Parallel Discrete Event Simulation for Electronic System-Level Design (Abstract)

Che-Wei Chang

R. Doemer

X. Han

W. Chen, Weiwei Chen is with the Center for Embedded Computer Systems University of California, Irvine, USA (email: weiwei.chen@uci.edu)

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Expedited-Compact Architecture for Average Scan Power Reduction (PDF)

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A New Approach for Automatic Test Pattern Generation in Register transfer Level Circuits (Abstract)

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Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms (Abstract)

V. Rana, V. Rana is with Embedded Systems Laboratory (ESL), EPFL, Lausanne, 1015, Switzerland.(email:rana@elet.polimi.it)

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LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing (Abstract)

L. Wang

X. Wen

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Reliability Analysis of Small Delay Defects Due to Via Narrowing in Signal Paths (Abstract)

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Dynamic Specification Testing and Diagnosis of High Precision Sigma-Delta ADCs (Abstract)

A. Chatterjee

A. Banerjee

S. Kook, S. Kook is with School of ECE, Georgia Tech, Atlanta, GA.

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Diverse Double Modular Redundancy: A New Direction for Soft Error Detection and Correction (Abstract)

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Organizational Dynamics: Understanding the Impact of Organizational Structure in Team Productivity (Abstract)

Michael Jassowski, Intel, Folsom

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Dispelling the Myths of Parallel Computing (Abstract)

P. H. Madden, P. H. Madden is with SUNY Binghamton Computer Science Department. (email: pmadden@acm.org)

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Multicore Algorithms for Transient Noise Simulation (Abstract)

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Handling Nondeterminism in Logic Simulation So That Your Waveform Can Be Trusted Again (Abstract)

Kai-hui Chang, Avery Design Systems , Andover

Hong-Zu Chou, SpringSoft, Hsinchu

Haiqian Yu, Teradyne Inc., North Reading

Dylan Dobbyn, Teradyne Inc., North Reading

Sy-Yen Kuo, National Taiwan University, Taipei

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To Thread Or Not To Thread? (Abstract)

U. Finkler

S. Hirsch

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Scan-based Speed-path Debug for a Microprocessor (Abstract)

Jing Zeng, AMD, austin

Ruifeng Guo, mentor graphics, wilsonville

Wu-Tung Cheng, mentor graphics, wilsonville

Michael Mateja, Advanced Micro Devices, Austin

Jing Wang, Advanced Micro Devices, Austin

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xMAS: Quick Formal Modeling of Communication Fabrics to Enable Verification (Abstract)

Satrajit Chatterjee, Intel, Hillsboro

Mike Kishinevsky, Intel , Hillsboro

Umit Ogras, Intel Corp. , Hillsboro

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Hardware IP Protection During Evaluation Using Embedded Sequential Trojan (Abstract)

Seetharam Narasimhan, Case Western Reserve University, Cleveland

Rajat Chakraborty, Indian Institute of Technology, Kharagpur, Kharagpur

Swarup Bhunia, Case Western Reserve University, Cleveland

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SAT-based Analysis of Sensitisable Paths (Abstract)

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Integrated Systems In The More-Than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components (Abstract)

Kaushik Roy, Purdue Univ, West Lafayette

Byunghoo Jung, Purdue University, West Lafayette

Dimitrios Peroulis, Purdue Univ, West Lafayette

Anand Raghunathan, Purdue Univ, West Lafayette

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Exploiting Parallelism by Data Dependency Elimination: A Case Study of Circuit Simulation Algorithms (Abstract)

L. He

F. Gong

R. Krishnan

H. Yu

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