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A New Approach for Automatic Test Pattern Generation in Register transfer Level Circuits
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ISSN: 0740-7475
| ASCII Text | x | ||
| M. Tabandeh, B. Alizadeh, Z. Navabi, "A New Approach for Automatic Test Pattern Generation in Register transfer Level Circuits," IEEE Design & Test of Computers, vol. 99, no. 1, pp. 1, , 5555. | |||
| BibTex | x | ||
| @article{ 10.1109/MDT.2012.2217471, author = {M. Tabandeh and B. Alizadeh and Z. Navabi}, title = {A New Approach for Automatic Test Pattern Generation in Register transfer Level Circuits}, journal ={IEEE Design & Test of Computers}, volume = {99}, number = {1}, issn = {0740-7475}, year = {5555}, pages = {1}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2217471}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - A New Approach for Automatic Test Pattern Generation in Register transfer Level Circuits IS - 1 SN - 0740-7475 SP EP EPD - 1 A1 - M. Tabandeh, A1 - B. Alizadeh, A1 - Z. Navabi, PY - 5555 KW - RTL Circuits KW - Automatic Testin KW - Canonical Representation KW - Test Pattern Generation VL - 99 JA - IEEE Design & Test of Computers ER - | |||
In this paper, we propose an approach to generate high-level test patterns from the arithmetic model of an RTL circuit using a hybrid canonical data structure based on a decision diagram. High-level simplified and fast symbolic path activation strategy as well as input justification is combined with test pattern generation for circuits under consideration. The current approach has been implemented for a range of small to large benchmark circuits. The results clearly demonstrate that tests generated using the proposed method have achieved high fault coverage for known sequential circuit benchmarks in very short CPU time and minimum memory usage.
Index Terms:
RTL Circuits,Automatic Testin,Canonical Representation,Test Pattern Generation
Citation:
M. Tabandeh, B. Alizadeh, Z. Navabi, "A New Approach for Automatic Test Pattern Generation in Register transfer Level Circuits," IEEE Design & Test of Computers, 06 Sept. 2012. IEEE computer Society Digital Library. IEEE Computer Society, <http://doi.ieeecomputersociety.org/10.1109/MDT.2012.2217471>
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