Advanced Search 
IEEE Design & Test of Computers
January 2012 (vol. 29 no. 1)
ISSN: 0740-7475
Table of Contents
Papers
Glenn Gulak, University of Toronto, Toronto, ON, Canada
Rajesh Gupta, University of California, San Diego, CA, USA
Gianluca Setti, University of Bologna, Italy
Yervant Zorian, Virage Logic,
pp. 5
Phil Nigh, Microelectronics Division, IBM Server & Technology Group,
pp. 6-7
Brady Benware, Mentor Graphics Corp., Wilsonville, OR, USA
Chris Schuermyer, Mentor Graphics Corp., Wilsonville, OR, USA
Manish Sharma, Mentor Graphics Corp., Wilsonville, OR, USA
Thomas Herrmann, GLOBALFOUNDRIES, Dresden, Germany
pp. 8-18
Sounil Biswas, Nvidia, Santa Clara,
Bruce Cory, Nvidia, Santa Clara,
pp. 19-27
Nathan Kupp, Yale University,
Yiorgos Makris, Electrical Engineering Department, The University of Texas at Dallas, Richardson, TX, USA
pp. 28-35
Ronald DeShawn Blanton, Advanced Chip Testing Laboratory, Carnegie Mellon University,
Wing Chiu Tam, Advanced Chip Testing Laboratory, Carnegie Mellon University,
Xiaochun Yu, Advanced Chip Testing Laboratory, Carnegie Mellon University,
Jeffrey E. Nelson, Advanced Chip Testing Laboratory, Carnegie Mellon University,
Osei Poku, Advanced Chip Testing Laboratory, Carnegie Mellon University,
pp. 36-47
Shyam Kumar Devarakond, Georgia Institute of Technology , Atlanta,
Shreyas Sen, Intel Circuit Research Lab , Hillsboro,
Soumendu Bhattacharya, Texas Instruments, Dallas,
Abhijit Chatterjee, Georgia Institute of Technology, Atlanta,
pp. 48-58
Stan Krolikoski, Cadence Design Systems,
pp. 68-71
Partha Pande, School of Electrical Engineering and Computer Science, Washington State University, Pullman,
pp. 76-77
Usage of this product signifies your acceptance of the Terms of Use.