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IEEE Design & Test of Computers
May/June 2011 (vol. 28 no. 3)
ISSN: 0740-7475
Table of Contents
Transaction-Level Validation of Multicore Architectures
Samar Abdi, Concordia University
Yonghyun Hwang, Qualcomm
Lochi Yu, Universidad de Costa Rica
Gunar Schirner, Northeastern University
Daniel D. Gajski, University of California, Irvine
pp. 10-19
Frédéric Pétrot, Grenoble Institute of Technology
Patrice Gerin, Kalray
Marius Gligor, Grenoble Institute of Technology
Mian-Muhammed Hamayun, Grenoble Institute of Technology
Hao Shen, Grenoble Institute of Technology
pp. 32-43
Perspectives
Zeljko Zilic, McGill University
Prabhat Mishra, University of Florida
Sandeep Shukla, Virginia Tech
pp. 52-53
Fault Tolerance Through Selective Hardening
Ilia Polian, University of Passau
John P. Hayes, University of Michigan, Ann Arbor
pp. 54-63
Postproduction Performance Calibration
Nathan Kupp, Yale University
He Huang, Yale University
Yiorgos Makris, Yale University,
Petros Drineas, Rensselaer Polytechnic Institute
pp. 64-75
Weiwei Chen, Electr. Eng. & Comput. Sci. Dept., Univ. of California, Irvine, CA, USA
Xu Han, Electr. Eng. & Comput. Sci. Dept., Univ. of California, Irvine, CA, USA
R Doemer, Electr. Eng. & Comput. Sci. Dept., Univ. of California, Irvine, CA, USA
pp. 20-31
Standards
Book Reviews
B Vermeulen, NXP Semicond., Netherlands
K Goossens, Electr. Eng. Dept., Eindhoven Univ. of Technol., Eindhoven, Netherlands
pp. 44-51
Conference Reports
Panel Summaries
The Road Ahead
Andrew B. Kahng, University of California, San Diego
pp. 86-89
CEDA Currents
TTTC Newsletter
DATC Newsletter
The Last Byte
Sandeep Shukla, Virginia Tech
Prabhat Mishra, University of Florida
Zeljko Zilic, McGill University
pp. 96
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