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A GALS Infrastructure for a Massively Parallel Multiprocessor
September-October 2007 (vol. 24 no. 5)
pp. 454-463
ASCII Text
x 
 
Luis A. Plana, Steve B. Furber, Steve Temple, Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang, "A GALS Infrastructure for a Massively Parallel Multiprocessor," IEEE Design & Test of Computers, vol. 24, no. 5, pp. 454-463, September-October, 2007.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2007.149,
author = {Luis A. Plana and Steve B. Furber and Steve Temple and Mukaram Khan and Yebin Shi and Jian Wu and Shufan Yang},
title = {A GALS Infrastructure for a Massively Parallel Multiprocessor},
journal ={IEEE Design & Test of Computers},
volume = {24},
number = {5},
issn = {0740-7475},
year = {2007},
pages = {454-463},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2007.149},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - A GALS Infrastructure for a Massively Parallel Multiprocessor
IS - 5
SN - 0740-7475
SP454
EP463
EPD - 454-463
A1 - Luis A. Plana,
A1 - Steve B. Furber,
A1 - Steve Temple,
A1 - Mukaram Khan,
A1 - Yebin Shi,
A1 - Jian Wu,
A1 - Shufan Yang,
PY - 2007
KW - massively parallel multiprocessor
KW - GALS
KW - Spinnaker
KW - neural modeling
KW - self-timed interconnect
VL - 24
JA - IEEE Design & Test of Computers
ER -
 
Luis A. Plana, University of Manchester
Steve B. Furber, University of Manchester
Steve Temple, University of Manchester
Mukaram Khan, University of Manchester
Yebin Shi, University of Manchester
Jian Wu, University of Manchester
Shufan Yang, University of Manchester
The Spinnaker (Spiking Neural Network Architecture) system for large-scale neural modeling is based on a scalable processor chip containing multiple ARM cores. Using a globally asynchronous, locally synchronous (GALS) approach allows custom, off-the-shelf IP to be readily integrated without significant timing-closure design effort. The ARM processors are used to simulate neurons, and generated neural events are carried over an on-chip, packet-switched fabric. This self-timed interconnect is also extended off chip to a provide chip-to-chip interconnect that scales to networks of thousands of chips.

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7. J. Wu and S. Furber, "Delay Insensitive Chip-to-Chip Interconnect Using Incomplete 2-of-7 NRZ Data Encoding," Proc. 18th UK Asynchronous Forum, University of Newcastle upon Tyne, 2006, pp. 16–19, http://async.org.ukukasyncforum18/.
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Index Terms:
massively parallel multiprocessor, GALS, Spinnaker, neural modeling, self-timed interconnect
Citation:
Luis A. Plana, Steve B. Furber, Steve Temple, Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang, "A GALS Infrastructure for a Massively Parallel Multiprocessor," IEEE Design & Test of Computers, vol. 24, no. 5, pp. 454-463, Sept.-Oct. 2007, doi:10.1109/MDT.2007.149
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