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A GALS Infrastructure for a Massively Parallel Multiprocessor
September-October 2007 (vol. 24 no. 5)
pp. 454-463
Luis A. Plana, University of Manchester
Steve B. Furber, University of Manchester
Steve Temple, University of Manchester
Mukaram Khan, University of Manchester
Yebin Shi, University of Manchester
Jian Wu, University of Manchester
Shufan Yang, University of Manchester
The Spinnaker (Spiking Neural Network Architecture) system for large-scale neural modeling is based on a scalable processor chip containing multiple ARM cores. Using a globally asynchronous, locally synchronous (GALS) approach allows custom, off-the-shelf IP to be readily integrated without significant timing-closure design effort. The ARM processors are used to simulate neurons, and generated neural events are carried over an on-chip, packet-switched fabric. This self-timed interconnect is also extended off chip to a provide chip-to-chip interconnect that scales to networks of thousands of chips.

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Index Terms:
massively parallel multiprocessor, GALS, Spinnaker, neural modeling, self-timed interconnect
Citation:
Luis A. Plana, Steve B. Furber, Steve Temple, Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang, "A GALS Infrastructure for a Massively Parallel Multiprocessor," IEEE Design & Test of Computers, vol. 24, no. 5, pp. 454-463, Sept.-Oct. 2007, doi:10.1109/MDT.2007.149
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