This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Leakage Minimization Technique for Nanoscale CMOS VLSI
July/August 2007 (vol. 24 no. 4)
pp. 322-330
Kyung Ki Kim, Northeastern University
Yong-Bin Kim, Northeastern University
Minsu Choi, University of Missouri-Rolla
Nohpill Park, Oklahoma State University, Stillwater
This article proposes a new heuristic approach to determine the input patterns that minimize leakage currents of nanometer CMOS circuits during sleep mode. The proposed approach uses a new macromodeling technique to characterize the minimum leakage current of each individual cell, considering fan-out effects, stack effect, and the interaction between gate-leakage and subthreshold currents. Experimental results shows that the methodology using the proposed macromodel provides less than a 4% error compared to Hspice simulation results.
Index Terms:
nanometer CMOS, cell characterization, leakage power, subthreshold leakage current, gate-tunneling current, input pattern generation
Citation:
Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Park, "Leakage Minimization Technique for Nanoscale CMOS VLSI," IEEE Design & Test of Computers, vol. 24, no. 4, pp. 322-330, July-Aug. 2007, doi:10.1109/MDT.2007.141
Usage of this product signifies your acceptance of the Terms of Use.