Design and CAD for Nanotechnologies
JULY-AUGUST 2007 (Vol. 24, No. 4) p. 300
0740-7475/07/$31.00 © 2007 IEEE

Published by the IEEE Computer Society
Design and CAD for Nanotechnologies
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Recent innovations in nanoscale devices offer the potential for greater information density and system functionality. However, these new devices mandate design parameters different from those applied to the current generation of scaled CMOS devices. These devices will also require different charge-control methods and evaluation metrics for parameters such as noise margin, threshold voltage, propagation delay, capacitance, and parasitics. Implementing these changes has obvious, profound implications for the operation of the complex circuits constructed from such devices. Yet, there is negligible progress toward mapping possible system designs on real nanodevice technologies.
Design methodologies and tools have obtained a tremendous degree of sophistication and predictive value, and have kept pace with shrinking device dimensions and changes in device specifications. There are advantages in using the power of these tools, insights, and methodologies to explore and define a context for evaluating next-generation nanoelectronic technologies. Without such a context, new nanoelectronic devices will continue to be evaluated against the metrics of existing scaled CMOS technologies; and, against those metrics, new technologies may always be found wanting. More important, without a common context of systems evaluation, it will be difficult to make early viability assessments of new nanoelectronic-device approaches, nor will it be possible to strategically guide the development of these new technologies.
This issue of IEEE Design & Test offers a special section on such topics. Our guest editors, Fabrizio Lombardi and Cecilia Metra, have selected three articles for this Special Section on Computer-Aided Design for Emerging Technologies, including an overview article on nanoscale devices and circuits. The other two articles cover the topics of leakage minimization for scaled CMOS and probabilistic testing for logic circuits in the nanometer realm.
Tutorial and surveys have been among the most popular types of articles in D&T, according to our readers. To identify timely tutorial topics and suitable authors, D&T has been collaborating with the Test Technology Educational Program (TTEP) of the IEEE Test Technology Technical Council (TTTC). Chaired by Dimitris Gizopoulos, TTEP offers a wide range of half-day and full-day tutorials at its conferences. Through this collaboration, the authors of some of the most successful tutorials managed by TTEP were invited to convert their presentations into D&T tutorial articles. "Practices in Mixed-Signal and RF IC Testing," by Salem Abdennadher and Saghir Shaikh, is the first in this tutorial series, and we are happy to include it in this issue of D&T.
This issue also contains five general-interest articles, addressing various design and test issues. One article proposes a mixed hardware-software solution for testing on-chip networks subject to crosstalk faults and single-event upsets (SEUs). Two other articles address the yield loss problems caused by delay testing. One of these suggests an interesting change to the scan-based delay test application protocol for yield improvement, and the other suggests generating special delay-test patterns to minimize yield loss. A software tool for process diagnosis, which is fully operational at industrial production sites, is described in yet another of these general-interest articles. Finally, there is an article describing a simulation tool for evaluating redundancy schemes used to repair embedded memories.








Tim Cheng
Editor in Chief
IEEE Design & Test