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Modeling Power Supply Noise in Delay Testing
May-June 2007 (vol. 24 no. 3)
pp. 226-234
Jing Wang, Texas A&M University
Duncan M. (Hank) Walker, Texas A&M University
Xiang Lu, P.A. Semi
Ananta Majhi, NXP Semiconductors
Bram Kruseman, NXP Semiconductors
Guido Gronthoud, NXP Semiconductors
Luis Elvira Villagra, NXP Semiconductors
Paul J.A.M. van de Wiel, NXP Semiconductors
Stefan Eichenberger, NXP Semiconductors
Excessive power supply noise can affect path delay in ICs. Silicon results show that filling of don't-care bits in test patterns can cause as much as 15% delay variation. Such extra delay may cause overkill during delay test. This article describes two types of low-cost noise models, compares them in model accuracy and application, and provides directions for model improvement. Excessive noise may come from compaction or filling during delay test generation. Experiments show how noise varies with different filling approaches, and how compaction is affected when the noise level for compacted tests is constrained.
Index Terms:
delay test, power supply noise model, compaction, filling
Jing Wang, Duncan M. (Hank) Walker, Xiang Lu, Ananta Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul J.A.M. van de Wiel, Stefan Eichenberger, "Modeling Power Supply Noise in Delay Testing," IEEE Design & Test of Computers, vol. 24, no. 3, pp. 226-234, May-June 2007, doi:10.1109/MDT.2007.76
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