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Design&Test
1997
Issue No. 1 - January-March
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IEEE Design & Test of Computers
January-March 1997 (vol. 14 no. 1)
ISSN: 0740-7475
Table of Contents
EIC Message
Keeping in touch: Reader survey results; planned e-mail survey
(Abstract)
pp. 4-5
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Interview-Design data standard
CFI leads development of design data standard
(Abstract)
J. Wilson
pp. 6,91
ABSTRACT
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News-JOLLY, BIST for embedded DRAM
News
(Abstract)
pp. 7,90
ABSTRACT
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Guest Editor's Introduction
Guest Editor's Introduction: Microprocessors Lead the Way in Complex Design
(HTML)
Marc E. Levitt
pp. 8-9
ABSTRACT
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Ultrasparc Testability
Designing UltraSparc for Testability
(Abstract)
Marc E. Levitt
pp. 10-17
ABSTRACT
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Memory Defect Mapping
Mapping and Repairing Embedded-Memory Defects
(Abstract)
Lynn Youngs
Siva Paramanandam
pp. 18-24
ABSTRACT
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Features
Alpha 21164 Testability Strategy
(Abstract)
Dilip K. Bhavsar
John H. Edmondson
pp. 25-33
ABSTRACT
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Prototyping the M68060 for Concurrent Verification
(Abstract)
Jainendra Kumar
pp. 34-41
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NREC: Risk Assessment and Planning of Complex Designs
(Abstract)
Margarida F. Jacome
Viktor Lapinskii
pp. 42-49
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Special Features
Testing Logic-Intensive Memory ICs on Memory Testers
(Abstract)
Robert Wu
Jerry Gerner
Richard Wheelus
Kevin Lew
pp. 50-54
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Collateral ASIC Test
(Abstract)
Al Bailey
Tim Lada
Jim Preston
pp. 55-63
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Impact of System Partitioning on Test Cost
(Abstract)
Ghassan Al-hayek
Yves Le Traon
Chantal Robach
pp. 64-74
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A D&T Roundtable
Hardware-Software Codesign
(Abstract)
pp. 75-83
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Panel Summaries-Asynchronous design, Intranets and EDA
Panel Summaries
(Abstract)
pp. 84-87
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Conference Reports-ATS 96, System Test Standards Committee
Conference Reports
(Abstract)
pp. 88-90
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DATC Newsletter
Design Automation Technical Committee Newsletter
(Abstract)
pp. 92-93
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TTTC Newsletter
Test Technology Tc Newsletter
(Abstract)
pp. 94-95
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The Last Byte-Teaching George about test
George learns test
(Abstract)
Scott Davidson
pp. 96
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