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Design&Test
1996
Issue No. 4 - Winter
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IEEE Design & Test of Computers
Winter 1996 (vol. 13 no. 4)
ISSN: 0740-7475
Table of Contents
News
News
(Abstract)
pp. 3-4,88
ABSTRACT
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Conference Reports
Second Therminic Workshop
(Abstract)
Bernard Courtois
pp. 5
ABSTRACT
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Keynotes
Designing in the multimedia era
(Abstract)
Harold S. Stone
pp. 6-7
ABSTRACT
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The future of IC design, testing, and manufacturing
(Abstract)
Wojciech Maly
pp. 8,89-91
ABSTRACT
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Features
FPGA Architectural Research: A Survey
(Abstract)
Stephen Brown
pp. 9-15
ABSTRACT
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Minimizing FPGA Interconnect Delays
(Abstract)
Stephen Brown
Muhammad Khellah
Zvonko Vranesic
pp. 16-23
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A Fault Injection Technique for VHDL Behavioral-Level Models
(Abstract)
Todd A. Delong
Barry W. Johnson
Joseph A. Profeta Iii
pp. 24-33
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Transmission Coefficient Correction for DACs
(Abstract)
Jacob M. Velixon
pp. 34-39
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BIST for D/A and A/D Converters
(Abstract)
Karim Arabi
Bozena Kaminska
Janusz Rzeszut
pp. 40-49
ABSTRACT
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Circular Self-Test Path for FSMs
(Abstract)
Fulvio Corno
Paolo Prinetto
Matteo Sonza Reorda
pp. 50-60
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IDDQ Testing: Issues Present and Future
(Abstract)
Jerry M. Soden
Charles F. Hawkins
pp. 61-65
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How ATE Planning Affects LSI Manufacturing Cost
(Abstract)
Koji Nakamae
Homare Sakamoto
Hiromu Fujioka
pp. 66-73
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A D&T Roundtable: Telecommunications System Design
(Abstract)
pp. 74-81
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IEEE Design & Test of Computers 1996 Annual Index, Volume 13
(Abstract)
pp. 82-85
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Author Guidelines
Author Guidelines IEEE Design & Test of Computers
(Abstract)
pp. 86-87
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DATC Newsletter
Design Automation Technical Committee Newsletter
(Abstract)
pp. 93
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TTTC Newsletter
Test Technology Tc Newsletter
(Abstract)
pp. 94-95
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The Last Byte
When tools cry wolf: Testability pitfalls of synthesized designs
(Abstract)
Robert C. Aitken
pp. 96
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