July/August 2008

Design in the Late- and Post-Silicon Eras

ISSUE HIGHLIGHTS:

Guest Editors' Introduction: System IC Design Challenges beyond 32 nm
by William H. Joyner Jr. and David C. Yeh, Semiconductor Research Corp.
This special issue features six articles on research efforts at the Gigascale Systems Research Center on systems architecture and design aspects of electronics systems in the late- and post-silicon eras, an interview with Intel Chair Craig Barrett, three sidebars by industry leaders, a Perspectives article, and a related Last Byte column.

The Last Byte
Who knew this "experiment" would be so successful?
Betsy Weitzman, Semiconductor Research Corp.
Focus Center Research Program executive director Betsy Weitzman looks back at the genesis of the FCRP, and looks forward to more groundbreaking research through multiuniversity collaboration and an industry-government-academia partnership.

SPECIAL FEATURE:

An interview with Intel Chair Craig Barrett

View Parts I and II of video highlights from the Craig Barrett interview on Computing Now

WEB EXTRAS

Conference Reports
1. 2008 IEEE Latin American Test Workshop
Victor Champac, National Institute for Astrophysics, Optics, and Electronics
The 9th Annual IEEE Latin American Test Workshop was held in Puebla, Mexico, on 17-20 February 2008. The technical program consisted of a keynote address, regular papers, invited talks, and tutorials. The regular papers were grouped into eight sessions, covering different test aspects, including yield optimization, design verification and validation, fault modeling, analog and mixed-signal test, BIST, online test, SoC test, single-event upset (SEU) modeling and simulation, and fault-tolerant architectures.
2. TTTC Best Doctoral Thesis Contest
Yiorgos Makris, Yale University
The 4th TTTC Best Doctoral Thesis Contest was held during the 26th IEEE VLSI Test Symposium in San Diego, California, on 28 April 2008. The aim of this competition is to promote and strengthen interaction between graduate students and the industry community. Students are given a chance to present their work to a panel of industry test experts, who evaluate it in terms of novelty and advancement of industry practice. The winner of the contest is invited to submit a paper to IEEE Design & Test and is awarded a $250 honorarium.

Panel Summaries
ITC 2007 panels
Yervant Zorian, Virage Logic
A key comment of the International Test Conference technical program, the panel sessions provide an informal and entertaining opportunity to explore emerging and controversial subjects in test technology and its practice. The ITC 2007 panel discussions featured a diverse group of industry and academic experts engaged in discussions and debates on a wide range of issues and subjects with audiences of energetic ITC attendees. In this column, the panel organizers capture the deliberations and results from their respective panels for the enjoyment of IEEE Design & Test readers.

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