This Article 
 Bibliographic References 
 Add to: 
An Event-Based Architecture Definition Language
September 1995 (vol. 21 no. 9)
pp. 717-734
This paper discusses general requirements for architecture definition languages, and describes the syntax and semantics of the subset of the Rapide language that is designed to satisfy these requirements. Rapide is a concurrent event-based simulation language for defining and simulating the behavior of system architectures. Rapide is intended for modelling the architectures of concurrent and distributed systems, both hardware and software. In order to represent the behavior of distributed systems in as much detail as possible, Rapide is designed to make the greatest posible use of event-based modelling by producing causal event simulations. When a Rapide model is executed it produces a simulation that shows not only the events that make up the model’s behavior, and their timestamps, but also which events caused other events, and which events happened independently. The architecture definition features of Rapide are described here: event patterns, interfaces, architectures and event pattern mappings. The use of these features to build causal event models of both static and dynamic architectures is illustrated by a series of simple examples from both software and hardware. Also we give a detailed example of the use of event pattern mappings to define the relationship between two architectures at different levels of abstraction. Finally, we discuss briefly how Rapide is related to other event-based languages.

[1] T. Amon and G. Borriello,“A simulator for timing behavior,” ACM/IEEE Design Automation Conf., vol. 28, no. 1, pp. 656-661, June 1991.
[2] Intermetrics Inc., Ada 9X Reference Manual.Cambridge, Mass.: Intermetrics Inc., June 1994. ANSI/ISO Draft International Standard.
[3] L.M. Augustin,D.C. Luckham,B.A. Gennart,Y. Huh,, and A.G. Stanculescu,Hardware Design and Simulation in VAL/VHDL. Kluwer Academic Publishers, 1990.
[4] T. Bolognesi and E. Brinksma,“Introduction to the ISO specification language LOTOS,” van Eijk et al., ed., The Formal Description Technique LOTOS.Amsterdam: North-Holland, 1989, pp. 23-73.
[5] G. Berry,P. Couronne,, and G. Gonthier,“Synchronous programming of reactive systems: An introduction toEsterel,” Technical Report 647, INRIA, Paris, Mar. 1987.
[6] D. Bryan,“Rapide-0.2 language and tool-set overview,” Technical Note CSL-TN-92-387, Computer Systems Lab, Stanford Univ., Feb. 1992.
[7] W.F. Clocksin and C.S. Mellish,Programming in Prolog, 2nd ed. New York: Springer-Verlag, 1984.
[8] M.A. Ellis and B. Stroustrup,The Annotated C++ Reference Manual.Reading, Mass.: Addison-Wesley, 1990.
[9] C.J. Fidge,“Timestamps in message-passing systems that preserve the partialordering,” Australian Computer Science Comm., vol. 10, no. 1, pp. 55-66, Feb. 1988.
[10] B.A. Gennart,“Automated analysis of discrete event simulations using eventpattern mappings,” PhD thesis, Stanford Univ., Apr. 1991. Also Stanford University Computer Systems Laboratory Technical Report No.CSL-TR-91-464.
[11] B.A. Gennart and D.C. Luckham,“Validating discrete event simulations using event patternmappings,” Proc. 29th Design Automation Conf., pp. 414-419.Los Alamitos, Calif.: IEEE CS Press, 1992.
[12] The Object Management Group, The Common Object Request Broker: Architecture and Specification, rev. 1.1 ed., Dec. 1991.
[13] C. Hewitt,“Description and theoretical analysis of planner,” PhD thesis, MIT, 1971.
[14] C.A.R. Hoare,“Communicating sequential processes,” Comm. of the ACM, vol. 21, no. 8, pp. 666-677, Aug. 1978.
[15] D. Katiyar,D. Luckham,, and J. Mitchell,“A type system for prototyping languages,” Proc. 21st ACM Symp. on Principles of Programming Languages, Portland, 1994.
[16] D.C. Luckham,D.P. Helmbold,S. Meldal,D.L. Bryan,, and M.A. Haberler,“Task sequencing language for specifying distributed Ada systems:TSL-1,” Proc. of PARLE: Conf. on Parallel Architectures and Languages Europe, June15-19, 1987. Lecture Notes in Computer Science, no. 259, vol. 2: Parallel Languages, pp. 444-463. Eindhoven, The Netherlands: Springer-Verlag, 1987.
[17] D.C. Luckham,J.J. Kenney,L.M. Augustin,J. Vera,D. Bryan,, and W. Mann,“Specification and analysis of system architecture usingRapide,” IEEE Transactions on Software Engineering, vol. 21, no. 4, pp. 336-355, Apr. 1995.
[18] D. C. Luckham,Programming with Specifications: An Introduction to Anna, a Language for Specifying Ada Programs. New York: Springer-Verlag, 1990.
[19] D.C. Luckham,J. Vera,D. Bryan,L. Augustin,, and F. Belz,“Partial orderings of event sets and their application toprototyping concurrent, timed systems,” J. of Systems and Software, vol. 21, no. 3, pp. 253-265, June 1993.
[20] D.C. Luckham,J. Vera,, and S. Meldal,“Three concepts of system architecture,” unpublished manuscript.
[21] F. Mattern,“Virtual time and global states of distributed systems,” M. Cosnard, ed., Proc. of Parallel and Distributed Algorithms.New York: Elsevier Science Publishers, 1988. Also in Report No. SFB124P38/88, Dept. of Computer Science,University of Kaiserslautern.
[22] S. Meldal,S. Sankar,, and J. Vera,“Exploiting locality in maintaining potential causality,” Proc. Tenth Annual ACM Symp. on Principles of Distributed Computing, pp. 231-239,New York, Aug. 1991. Washington, D.C.: ACM Press. Also Stanford Univ. Computer Systems Laboratory Technical Report No.CSL-TR-91-466.
[23] R. Milner,M. Tofte,, and R. Harper,The Definition of Standard ML.Cambridge, Mass.: MIT Press, 1990.
[24] J.A. Robinson,“A machine-oriented logic based on the resolution principle,” J. of the ACM, vol. 12, no. 1, pp. 23-41, Jan. 1965.
[25] Rapide Design Team, The Rapide-1 Executable Language Reference Manual. Program Analysis and Verification Group, Computer Systems Lab.,Stanford University, version 1 ed., Oct. 1994.
[26] Rapide Design Team, The Rapide-1 Specification Language Reference Manual. Program Analysis and Verification Group, Computer Systems Lab.,Stanford University, version 1 ed., Oct. 1994.
[27] Rapide Design Team, The Rapide-1 Types Reference Manual. Program Analysis and Verification Group, Computer Systems Lab.,Stanford University, version 1 ed., Oct. 1994.
[28] D.E. Thomas and P.R. Moorby,The Verilog Hardware Description Language. Kluwer Academic Publishers, 1991.
[29] IEEE, Inc., IEEE Standard VHDL Language Reference Manual, IEEE Standard 1076-1987. Los Alamitos, Calif.: IEEE CS Press, 1987.
[30] X/Open Company Ltd., Distributed Transaction Processing: The Peer-to-Peer Specification, snapshot. Reading, Berkshire, England: X/Open Company Ltd., 1992.

Index Terms:
Rapide, architecture definition languages, partially ordered event sets, architecture, prototyping, concurrency, simulation, formal constraints, event patterns, causality.
David C. Luckham, James Vera, "An Event-Based Architecture Definition Language," IEEE Transactions on Software Engineering, vol. 21, no. 9, pp. 717-734, Sept. 1995, doi:10.1109/32.464548
Usage of this product signifies your acceptance of the Terms of Use.