Issue No.07 - July (1995 vol.21)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/32.392980
An accurate and safe estimation of a task’s worst case execution time (WCET) is crucial for reasoning about the timing properties of real-time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is affected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in analyzing the WCETs of tasks. To analyze the timing effects of RISC’s pipelined execution and cache memory, we propose extensions to the original timing schema where the timing information associated with each program construct is a simple time-bound. In our approach, associated with each program construct is worst case timing abstraction, (WCTA), which contains detailed timing information of every execution path that <it>might</it> be the worst case execution path of the program construct. This extension leads to a revised timing schema that is similar to the original timing schema except that concatenation and pruning operations on WCTAs are newly defined to replace the <tt>add</tt> and <tt>max</tt> operations on time-bounds in the original timingschema. Our revised timing schema accurately accounts for the timing effects of pipelined execution and cache memory not only within but also across program constructs. This paper also reports on preliminary results of WCET analysis for a RISC processor. Our results show that tight WCET bounds (within a maximum of about 30% overestimation) can be obtained by using the revised timing schema approach.
Cache memory, pipelined execution, real-time system, RISC processor, worst case execution time.
Young Hyun Bae, Gyu Tae Jang, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Kunsoo Park, Soo-Mook Moon, Chong Sang Kim, "An Accurate Worst Case Timing Analysis for RISC Processors", IEEE Transactions on Software Engineering, vol.21, no. 7, pp. 593-604, July 1995, doi:10.1109/32.392980