This Article 
 Bibliographic References 
 Add to: 
An Accurate Worst Case Timing Analysis for RISC Processors
July 1995 (vol. 21 no. 7)
pp. 593-604
An accurate and safe estimation of a task’s worst case execution time (WCET) is crucial for reasoning about the timing properties of real-time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is affected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in analyzing the WCETs of tasks. To analyze the timing effects of RISC’s pipelined execution and cache memory, we propose extensions to the original timing schema where the timing information associated with each program construct is a simple time-bound. In our approach, associated with each program construct is worst case timing abstraction, (WCTA), which contains detailed timing information of every execution path that might be the worst case execution path of the program construct. This extension leads to a revised timing schema that is similar to the original timing schema except that concatenation and pruning operations on WCTAs are newly defined to replace the add and max operations on time-bounds in the original timingschema. Our revised timing schema accurately accounts for the timing effects of pipelined execution and cache memory not only within but also across program constructs. This paper also reports on preliminary results of WCET analysis for a RISC processor. Our results show that tight WCET bounds (within a maximum of about 30% overestimation) can be obtained by using the revised timing schema approach.

[1] A.V. Aho, R. Sethi, and J.D. Ullman, Compilers, Principles, Techniques and Tools.New York: Addison-Wesley, 1985.
[2] R. Arnold, F. Mueller, D. Whalley, and M. Harmon, “Bounding Worst-Case Instruction Cache Performance,” Proc. 15th IEEE Real-Time Systems Symp., pp. 172-181, Dec. 1994.
[3] Y.H. Bae,“Data cache analysis techniques for real-time systems,” Masters thesis, Seoul National University, Korea, 1995.
[4] J.-Y. Choi,I. Lee,, and I. Kang,“Timing analysis of superscalar processor programs using ACSR,” Proc. 11th IEEE Workshop on Real-Time Operating Systems and Software, pp. 63-67, May 1994.
[5] F. Chow and J.L. Hennessy,“Register allocation by priority-based coloring,” Proc. ACM SIGPLAN’84 Symp. Compiler Construction, pp. 222-232, 1984.
[6] C.N. Fischer and R.J. LeBlanc,Crafting a Compiler with C.Redwood City, Calif.: The Benjamin/Cummings Publishing Co., Inc., 1991.
[7] C.W. Fraser and D.R. Hanson,“A code generation interface for ANSI C,” Tech. Report CSL-TR-270-90, Dept. of Computer Science, Princeton Univ., 1990.
[8] E. Harcourt,J. Mauney,, and T. Cook,“High-level timing specification of instruction-level parallel processors,” Tech. Report TR-93-18, Dept. of Computer Science, North Carolina State Univ., 1993.
[9] M.G. Harmon, T.P. Baker, and D.B. Whalley, “A Retargetable Technique for Predicting Execution Time,” Proc. 11th IEEE Real-Time Systems Symp., pp. 68-77, Dec. 1992.
[10] J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann, San Mateo, Calif., 1990.
[11] M.D. Hill, Aspects of Cache Memory and Instruction Buffer Performance, PhD thesis, UCB/CSD 87/381, Univ. of California at Berkeley, Nov. 1987.
[12] G. Kane and J. Heinrich, MIPS RISC Architecture, Prentice-Hall, Englewood Cliffs, N.J., 1992.
[13] R.M. Karp,“A characterization of the minimum cycle mean in a digraph,” Discrete Math., vol. 23, pp. 309-311, 1978.
[14] R.M. Keller, "Look-Ahead Processors," Computing Surveys, Vol. 7, No. 4, 1975, pp. 177-195.
[15] D.B. Kirk, “SMART (Strategic Memory Allocation for Real-Time) Cache Design,” Proc. 10th Real-Time Systems Symp., pp. 229–237, Dec. 1989.
[16] P.M. Kogge,The Architecture of Pipelined Computers. Hemisphere Publishing Corp., 1981.
[17] S.-S. Lim,“Instruction cache and pipelining analysis technique for real-time systems,” Masters thesis, Seoul National University, Korea, 1995.
[18] J.-C. Liu and H.-J. Lee,“Deterministic upperbounds of the worst-case execution times of cached programs,” Proc. 15th IEEE Real-Time Systems Symp., pp. 182-191, 1994.
[19] A. Mok,“Evaluating tight execution time bounds of programs by annotations,” Proc. Sixth IEEE Workshop on Real-Time Operating Systems and Software, pp. 74-80, 1989.
[20] K. Narasimhan and K.D. Nilsen,“Portable execution time analysis for RISC processors,” Proc. Workshop Architectures for Real-Time Applications, Apr. 1994.
[21] D. Niehaus,E. Nahum,, and J.A. Stankovic,“Predictable real-time caching in the Spring System,” Proc. Eighth IEEE Workshop on Real-Time Operating System and Software, pp. 76-80, 1991.
[22] C.Y. Park, "Predicting Deterministic Execution Times of Real-Time Programs," PhD thesis, Univ. of Washington, Seattle, Aug. 1992.
[23] C. Park, "Predicting Program Execution Times by Analyzing Static and Dynamic Program Paths," J. Real-Time Systems, vol. 5, no. 1, pp. 31-62, Mar. 1993.
[24] C.Y. Park and A.C. Shaw, "Experiments with a Program Timing Tool Based on Source-Level Timing Schema," Proc. IEEE Real-Time Systems Symp., IEEE, Piscataway, N.J., Dec. 1990, pp. 72-81.
[25] P. Puschner and C. Koza, "Calculating the Maximum Execution Time of Real-Time Programs," J. Real-Time Systems, vol. 1, no. 2, pp. 159-176, Sept. 1989.
[26] J. Rawat,“Static analysis of cache performance for real-time programming,” Masters thesis, Iowa State Univ., 1993.
[27] B.-D. Rhee,S. L. Min,, and H. Shin,“Retargetable timing analyzer for RISC processors,” Proc. First Int’l Workshop Real-Time Comput. Systems and Applications., pp. 76-79, Dec. 1994.
[28] A.C. Shaw, "Reasoning About Time in Higher-Level Language Software," IEEE Trans. Software Eng., vol. 15, no. 7, pp. 875-889, 1989.
[29] A. Stoyenko,"A Real-Time Language with a Schedulability Analyzer," Doctoral dissertation CSRI-206, Univ. of Toronto, Dec. 1987.
[30] A. Wolfe,“Software-based cache partitioning for real-time applications,” Proc. Third Workshop Responsive Computer Systems, Sept. 1993.
[31] N. Zhang,A. Burns,, and M. Nicholson,“Pipelined processors and worst-case execution times,” Real-Time Systems J., vol. 5, no. 4, pp. 319-343, Oct. 1993.

Index Terms:
Cache memory, pipelined execution, real-time system, RISC processor, worst case execution time.
Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Kunsoo Park, Soo-Mook Moon, Chong Sang Kim, "An Accurate Worst Case Timing Analysis for RISC Processors," IEEE Transactions on Software Engineering, vol. 21, no. 7, pp. 593-604, July 1995, doi:10.1109/32.392980
Usage of this product signifies your acceptance of the Terms of Use.