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Engineering and Analysis of Fixed Priority Schedulers
September 1993 (vol. 19 no. 9)
pp. 920-934

Scheduling theory holds great promise as a means to a priori validate timing correctness of real-time applications. However, there currently exists a wide gap between scheduling theory and its implementation in operating system kernels running on specific hardware platforms. The implementation of any particular scheduling algorithm introduces overhead and blocking components which must be accounted for in the timing correctness validation process. This paper presents a methodology for incorporating the costs of scheduler implementation within the context of fixed priority scheduling algorithms. Both event-driven and timer-driven scheduling implementations are analyzed. We show that for the timer-driven scheduling implementations the selection of the timer interrupt rate can dramatically affect the schedulability of a task set, and we present a method for determining the optimal timer rate. We analyzed both randomly generated and two well-defined task sets and found that their schedulability can be significantly degraded by the implementation costs. Task sets that have ideal breakdown utilization over 90% may not even be schedulable when the implementation costs are considered. This work provides a first step toward bridging the gap between real-time scheduling theory and implementation realities. This gap must be bridged for any meaningful validation of timing correctness properties of real-time applications.

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Index Terms:
fixed priority schedulers; timing correctness; real-time applications; scheduling theory; operating system kernels; hardware platforms; validation process; blocking components; fixed priority scheduling algorithms; timer-driven scheduling; event-driven scheduling;schedulability; optimal timer rate; operating systems (computers); real-time systems; scheduling
Citation:
D.I. Katcher, H. Arakawa, J.K. Strosnider, "Engineering and Analysis of Fixed Priority Schedulers," IEEE Transactions on Software Engineering, vol. 19, no. 9, pp. 920-934, Sept. 1993, doi:10.1109/32.241774
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