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Estimating the Speedup in Parallel Parsing
July 1990 (vol. 16 no. 7)
pp. 677-683

A method for estimating the speedup for asynchronous bottom-up parallel parsing is presented. Two models for bottom-up parallel parsing are proposed, and the speedup for each of the two models is estimated. The speedup obtained for model A is a very close to the simulation result already available in literature; however, the model is restrictive because it can only communicate with its immediate left and right neighbors. This increases the processor coordination and interprocessor communication times. Model B, while showing a greater speedup time, is expensive to construct when the number of processors is large.

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Index Terms:
speedup estimation; parallel parsing; asynchronous bottom-up; models; simulation result; processor coordination; interprocessor communication; grammars; parallel algorithms; program compilers.
Citation:
D. Sarkar, N. Deo, "Estimating the Speedup in Parallel Parsing," IEEE Transactions on Software Engineering, vol. 16, no. 7, pp. 677-683, July 1990, doi:10.1109/32.56094
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