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Memory Access Dependencies in Shared-Memory Multiprocessors
June 1990 (vol. 16 no. 6)
pp. 660-673

The presence of high-performance mechanisms in shared-memory multiprocessors such as private caches, the extensive pipelining of memory access, and combining networks may render a logical concurrency model complex to implement or inefficient. The problem of implementing a given logical concurrency model in such a multiprocessor is addressed. Two concurrency models are considered, and simple rules are introduced to verify that a multiprocessor architecture adheres to the models. The rules are applied to several examples of multiprocessor architectures.

[1] Special Session on Commercial Cache-Based Multiprocessors, inProc. 12th Int. Symp. Computer Architecture, June 1985, pp. 208- 240.
[2] G. Tucker, "The IBM 3090 system: An overview,"IBM Syst. J., vol. 25, no. 1, pp. 4-19, Jan. 1986.
[3] S. C. Chen, "Large-scale and high-speed multiprocessor system for scientific applications--CRAY-X-MP-2 series," inProc. NATO Advanced Research Workshop High Speed Computation, Nuclear Research Center, Julich, West Germany, June 1983.
[4] D. Gajski, D. Kuck, D. Lawrie, and A. Sameh, "Cedar-A large scale multiprocessor,"Comput. Architecture News, vol. 11, no. 1, pp. 7-11, Mar. 1983.
[5] A. Gottliebet al., "The NYU ultracomputer--Designing an MIMD shared memory parallel computer,"IEEE Trans. Comput., vol. C-32, no. 2, pp. 175-189, Feb. 1983.
[6] G. F. Pfisteret al., "The IBM Research parallel processor prototype (RP3): Introduction and architecture," inProc. 1985 Int. Conf. Parallel Processing, Aug. 1985, pp. 764-771.
[7] G. R. Andrews and F. B. Schneider, "Concepts and notations for concurrent programming,"ACM Comput. Surveys, vol. 15, no. 1, pp. 3-43, Mar. 1983.
[8] L. Lamport, "A new solution of Dijkstra's concurrent programming problem,"Commun. ACM, vol. 17, no. 8, pp. 453-455, 1974.
[9] E. W. Dijkstra, "Solution of a problem in concurrent programming control,"Commun. ACM, vol. 8, pp. 569-569, Sept. 1965.
[10] D. Knuth, "Additional comments on a problem in concurrent control,"Commun. ACM, vol. 9, no. 5, pp. 321-322, 1966.
[11] L. Lamport, "Proving the correctness of multiprocess programs,"IEEE Trans. Software Eng., vol. SE-3, no. 2, pp. 125-143, Mar. 1977.
[12] M. Dubois, C. Scheurich, and F. Briggs, "Synchronization, coherence, and event ordering in multiprocessors,"Computer, vol. 21, no. 2, pp. 9-21, Feb. 1988.
[13] W. D. Connors, "The IBM 3033: An inside look,"Datamation, pp. 198-218, May 1979.
[14] B. M. Bean, "Bias filter memory for filtering out unnecessary interrogations of cache directories in a multiprocessor system," U.S. Patent 4 142 234, Feb. 27, 1979.
[15] J.R. Goodman, "Using Cache Memory to Reduce Processor Memory Traffic,"Proc. 10th Symp. Computer Architecture, IEEE CS Press, Los Alamitos, Calif., Order No. 473 (microfiche only), 1983, pp. 124-131.
[16] M. Dubois and F. A. Briggs, "Effects of cache coherency in multiprocessors,"IEEE Trans. Comput., vol. C-31, no. 11, pp. 1083- 1099, Nov. 1982.
[17] J. Archibald and J.-L. Baer, "An evaluation of cache coherence solutions in shared-bus multiprocessors," Dep. Comput. Sci., Univ. Washington, Seattle, Tech. Rep. 85-10-05, Oct. 1985.
[18] C. Scheurich and M. Dubois, "Dependency and Hazard Resolution in Multiprocessors,"Proc. 14th Int'l Symp. Computer Architecture, IEEE CS Press, Los Alamitos, Calif., Order No. 776, 1987, pp. 234-243.
[19] D. Kroft, "Lockup-free instruction fetch/prefetch cache organization," inProc. 8th Annu. Symp. Comput. Architecture, June 1981, pp. 81-87.
[20] P. M. Kogge,The Architecture of Pipelined Computers. New York: McGraw-Hill, 1981.
[21] L. Lamport, "How to make a multiprocessor computer that correctly executes multiprocess programs,"IEEE Trans. Comput., vol. C-28, no. 9, pp. 690-691, Sept. 1979.
[22] L. M. Censier and P. Feautrier, "A solution to coherence problems in multicache systems,"IEEE Trans. Comput., vol. C-27, no. 12, pp. 1112-1118, Dec. 1978.
[23] L. Lamport, "Time, clocks, and the ordering of events in a distributed system,"Commun. ACM, vol. 21, no. 7, pp. 558-565, July 1978.
[24] K. Hwang and F. A. Briggs,Computer Architecture and Parallel Processing. New York: McGraw-Hill, 1984.
[25] W. Crowther, J. Goodhue, E. Starr, R. Thomas, W. Milliken, and T. Blackadar, "Performance measurements on the 128-node butterfly parallel processor," inProc. 1985 Int. Conf. Parallel Processing, Aug. 1985, pp. 531-540.
[26] "Symmetry technical summary," Sequent Computer Systems Inc., Beaverton, OR, 1987.
[27] A. Smith, "Cache Memories,"Computing Surveys, Vol. 14, No. 3, Sept. 1982, pp. 473- 530.
[28] C. Scheurich and M. Dubois, "Concurrent miss resolution in multiprocessor caches," inProc. 1988 Int. Conf. Parallel Processing, Aug. 1988, pp. 118-125.
[29] W. W. Collier, "Architectures for systems of parallel processes," IBM Corp. Tech. Rep. TR00.3253, Jan. 27, 1984.
[30] L. Lamport, "The mutual exclusion problem: Part I--A theory of interprocess communication,"J. ACM, vol. 33, no. 2, pp. 313-326, 1986.
[31] L. Rudolph and Z. Segall, "Dynamic decentralized cache schemes for MIMD parallel processors," inProc. 11th Int. Symp. Computer Architecture, 1984, pp. 340-347.
[32] W. C. Brantley, K. P. Mc Auliffe, and J. Weiss, "RP3 processormemory element," inProc. 1985 Int. Conf. Parallel Processing, Aug. 1985, pp. 782-789.
[33] F. A. Briggs and M. Dubois, "Effectiveness of private caches in multiprocessors with parallel-pipelined memories,"IEEE Trans. Comput., vol. C-32, no. 1, pp. 48-59, Jan. 1983.
[34] F. A. Briggs, "Effects of buffered memory requests in multiprocessor systems," inProc. ACM/Sigmetrics Conf. Simulation, Measurements, and Modeling of Computer Systems, May 1979, pp. 73-81.
[35] C.-Y. Chin and K. Hwang, "Packet-switching networks for multiprocessor and data-flow computers," inProc. 11th Symp. Computer Architecture, June 1984, pp. 99-109.
[36] P. Bitar and A. Despain, "Multiprocessor Cache Synchronization: Issues, Innovations, Evolution,"Proc. 13th ISCA, June 1986, pp. 424-442.
[37] L. Philipson, B. Nilsson, and B. Breidegard, "A communication structure for a multiprocessor computer with distributed global memory," inProc. 10th Int. Symp. Comput. Architecture, Stockholm, sweden, June 1983, pp. 334-340.
[38] E. F. Gehringer, A. K. Jones, and Z. Z. Segall, "The Cm*testbed,"Computer, pp. 40-53, Oct. 1982.
[39] C. E. Scheurich, "Access ordering and coherence in shared memory multiprocessors," Ph.D. dissertation, Dep. Comput. Eng., Tech. Rep. CENG 89-19, Univ. Southern California, May 1989.

Index Terms:
memory access dependencies; shared-memory multiprocessors; private caches; pipelining; logical concurrency model; rules; multiprocessor architectures; multiprocessing systems; multiprogramming; storage allocation.
M. Dubois, C. Scheurich, "Memory Access Dependencies in Shared-Memory Multiprocessors," IEEE Transactions on Software Engineering, vol. 16, no. 6, pp. 660-673, June 1990, doi:10.1109/32.55094
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