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Experimentally Characterizing the Behavior of Multiprocessor Memory Systems: A Case Study
February 1990 (vol. 16 no. 2)
pp. 216-223

It is demonstrated how the behavior of a cache-based multi-vector-processor memory system can be systematically characterized and its performance experimentally correlated with key features of the address stream. The approach is based on the definition of a family of parameterized kernels used to explore specific aspects of the memory system's performance. The empirical results from this kernel suite provide the data from which architectural or algorithmic characteristics can be studied. The results of applying the approach to an Alliant FX/8 are presented and evaluated.

[1] W. Abu-Sufah and A. Kwok, "Performance prediction tools for Cedar: A multiprocessor supercomputer," inProc. 12th Int. Symp. Computer Architecture, 1985, pp. 406-413.
[2] J. Andrews, D. Lavery, and R. Iyer, "A measurement based study of cache contention in a shared memory multiprocessor," Univ. Illinois, CSL Rep., 1987.
[3] D. H. Bailey, "Vector computer memory bank contention,"IEEE Trans. Computers, vol. C-36, pp. 293-298, Mar. 1987.
[4] I. Bucher and M. Simmons, "A close look at vector performance of register-to-register vector computers and a new model," inProc. 1987 ACM SIGMETRICS, 1987, pp. 39-45.
[5] D. Calahan, "Performance evaluation of static and dynamic memory systems on the Cray-2," inProc. 1988 Int. Conf. Supercomputing, ACM Press, 1988, pp. 519-524.
[6] T. Cheung and J. Smith, "An analysis of the Cray X-MP memory system," inProc. Int. Conf. Parallel Processing, Aug. 1984, pp. 494-505.
[7] K. Gallivan, W. Jalby, and D. Gannon, "On the problem of optimizing data transfers for complex memory systems," inProc. 1988 ACM Int. Conf. Supercomput., St. Malo France, July 1988, pp. 238,253.
[8] K. Gallivan, D. Gannon, W. Jalby, A. Malony, and H. Wijshoff, "Behavoral characterization of multiprocessor memory systems: A case study," Univ. Illinois at Urbana-Champaign, CSRD Rep. 808, Oct. 1988.
[9] K. Gallivan, W. Jalby, A. Malony, and H. Wijshoff, "Performance prediction of loop constructs on multiprocessor hierarchical memory systems," inProc. 1989 Int. Conf. Supercomputing, ACM Press, 1989, pp. 433-442.
[10] K. Gallivan, W. Jalby, U. Meier, and A. Sameh, "The impact of hierarchical memory systems on linear algebra algorithm design,"Int. J. Supercomput. Applicat., vol. 2, no. 1, pp. 12-48, Spring 1988.
[11] D. Gannon, W. Jalby, and K. Gallivan, "Strategies for Cache and Local Memory Management by Global Program Transformation,"J. Parallel and Distributed Computing, Vol. 5, No. 5, Oct. 1988, pp. 587-616.
[12] G. Phister and A. Norton, "Hot spot contention and combining in multistage interconnection networks," inProc. Int. Conf. Parallel Processing, 1985, pp. 790-797.
[13] Y. Saad and H.A.G. Wijshoff, "A Benchmark Package for Sparse Matrix Computations,"Proc. Int'l Conf. Supercomputing, ACM, New York, 1988, pp. 500-509.

Index Terms:
behavior analysis; performance analysis; multiprocessor memory systems; cache-based multi-vector-processor; address stream; parameterized kernels; algorithmic characteristics; Alliant FX/8; buffer storage; multiprocessing systems; program testing; storage management.
Citation:
K. Gallivan, D. Gannon, W. Jalby, A. Malony, H. Wijshoff, "Experimentally Characterizing the Behavior of Multiprocessor Memory Systems: A Case Study," IEEE Transactions on Software Engineering, vol. 16, no. 2, pp. 216-223, Feb. 1990, doi:10.1109/32.44384
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