This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
On the Minimization of Loads/Stores in Local Register Allocation
October 1989 (vol. 15 no. 10)
pp. 1252-1260

[1] A. V. Aho, R. Sethi, and J. D. Ullman,Compilers: Principles, Techniques, and Tools. Reading, MA: Addison-Wesley, 1986.
[2] F. E. Allen and J. Cocke, "A catalogue of optimizing transformations," inDesign and Optimization of Compilers. Englewood Cliffs, NJ: Prentice-Hall, 1972.
[3] F. E. Allen, "The history of language processor technology in IBM,"IBM J. Res. Develop., vol. 25, Sept. 1981.
[4] M. Auslander and M. Hopkins, "An overvier of the PL.8 compiler," inProc. ACM SIGPLAN '82 Symp. Compiler Construct., 1982.
[5] J. W. Backuset al., "The FORTRAN automatic coding system,"Programming Systems and Languages, S. Roan, Ed. New York: McGraw-Hill, 1967, pp. 29-47.
[6] L. A. Bclady, "A study of replacement algorithms for a virtual-storabe computer,"IBM Syst. J., vol. 5, no. 2, 1966.
[7] G. J. Chaitinet al., "Register allocation via coloring,"Comput, Lang., vol. 6, 1981.
[8] G. J. Chaitin, "Register allocation and spilling via graph coloring,"SIGPLAN Not., vol. 17, no. 6, pp. 98-105, 1982.
[9] F. Chow and J. Hennessy, "Register allocation by priority-based coloring,"SIGPLAN Not., vol. 19, no. 6, pp. 222-232, 1984.
[10] J. Cocke and J. T. Schwartz, "Programming language and their compilers," Coutant Inst. Math. Sci., NYU, 1970.
[11] D. S. Coutant, C. L. Hammond, and J. W. Kelly, "Compilers for the new generation of Hewlett-Packard computers," inProc. IEEE Spring Compcon Conf., 1986.
[12] J. Davidson and C. Fraser, "Register allocation and exhaustive peephole optimization."Software--Practice and Experience, Sept. 1984.
[13] W. H. E. Day, "Compiler assignment of data to registers,"IBM Syst. J., vol. 9, no. 4, pp. 281-317, 1970.
[14] J. J. Dongarra and A. R. Jinds, "Unrolling loops in Fortran,"Software--Practice and Experience, vol. 9, no. 3, pp. 219-226, Mar. 1979.
[15] J. R. Ellis, "Bulldog: A compiler for VLIW architectures," Ph.D. dissertation, Dep. Comput. Sci., Yale University.
[16] C. N. Fischer and R. J. LeBlanc,Crafting a Compiler. Menlo Park, CA: Benjamin-Cummings, 1988.
[17] J. Fisher, "Trace scheduling: A technique for global microcode compaction,"IEEE Trans. Comput., vol. C-30, no. 7, July 1981.
[18] R. A. Freiburghouse, "Register allocation via usage counts,"Commun. ACM, vol. 17, no. 11, pp. 638-642, 1974.
[19] P. B. Gibbons and S. S. Muchnick, "Efficicnt instruction scheduling for a pipelined architecture," inProc. SIGPLAN '86 Symp. Compiler Construction, June 1986.
[20] W. Harrison, "A class of register allocation algorithms," IBM Res. Rep. RC 5342, 1975.
[21] J. Hennessy and T. Gross, "Postpass Code Optimization of Pipeline Constraints,"ACM Trans. Programming Languages and Systems, Vol. 5, No. 3, New York, July 1983, pp. 422-448.
[22] L. P. Horwitz, R. M. Karp, R. E. Miller, and S. Winograd, "Index register allocation,"J. ACM, vol. 13. no. 1, pp. 43-61, Jan. 1966.
[23] P. Hsu, "Highly concurrent scalar processing," Ph.D. dissertation, Dep. Comput. Sci., Univ. of Illinois at Urbana-Champaign, 1985.
[24] W. C. Hsu, "Register allocation and code scheduling for load/store architectures," Univ. Wisconsin, Comput. Sci. Tech. Rep. 722, Oct. 1987.
[25] K. Kennedy, "Index register allocation in straight line code and simple loops," inDesign and Optimization of Compilers, Englewood Cliffs, NJ: Prentice-Hall, 1972.
[26] J. Kim, "Spill placement optimization in register allocation for compilers," IBM, Res. Rep. RC 7251, 1978.
[27] D. Kranz et al., "Orbit: An Optimizing Compiler for Scheme,"Proc. SIGPlan '86 Symp. Compiler Construction, ACM, June 1986, pp. 219-233.
[28] B. W. Leverett, "Register allocation in optimizing compilers," Ph.D. dissertation, Carnegie-Mellon Univ., Rcp. CMU CS-81-103, Feb. 1981.
[29] F. Luccio, "A comment on index in register allocation,"Commun. ACM, vol. 10, no. 9, pp. 572-574, 1967.
[30] M. D. MacLaren, "Inline routines in VAXELN Pascal,"SIGPLAN Not., vol. 19, no. 6, pp. 266-275, 1984.
[31] N. H. Madhavji and I. R. Wilson, "CRAY Pascal," inProc. SIGPLAN '82 Symp. Compiler Construction, 1982.
[32] F. H. McMahon, "FORTRAN CPU performance analysis," Lawrence Livermore Laboratories, 1972.
[33] M. Moshier and V. Rajlich, "Slumlord: A register allocation and its statistical analysis," Univ. Michigan, Tech, Rep. CRL-TR-2-85, 1985.
[34] D. A. Patterson, "Reduced instruction set computers,"Commun. ACM, vol. 28, pp. 8-21, Jan. 1985.
[35] M. L. Powell, "A portable optimizing compiler for Modula-2,"SIGPLAN Not., vol. 19, vol. 6, pp. 310-318, 1984.
[36] R. Rustin,Design and Optimization of Compilers. Englewood Cliffs, NJ: Prentice-Hall, 1972.
[37] R. W. Scheifler, "An analysis of inline substitution for a structured programming language,"Commun. ACM, vol. 20, no. 9, pp. 647-654, 1977.
[38] R. Sethi and J. D. Ullman, "The generation of optimal code for arithmetic expressions,"J. ACM, vol. 17, pp. 715-728, Oct. 1970.
[39] R. Sedgewick,Algorithms. Reading, MA, Addison-Wesley, 1983.
[40] S. Weiss and J.E. Smith, "A Study of Scalar Compilation Techniques for Pipelined Supercomputers,"Proc. Second Int'l Conf. Architectural Support for Programming Languages and Operating Systems(ASPLOS-II), CS Press, Los Alamitos, Calif., Order No. 805, 1987, pp. 105-109.

Index Terms:
Computer architecture; local register allocation; program esptimization
Citation:
Wei-Chung Hsu, C.N. Fischer, J.R. Goodman, "On the Minimization of Loads/Stores in Local Register Allocation," IEEE Transactions on Software Engineering, vol. 15, no. 10, pp. 1252-1260, Oct. 1989, doi:10.1109/TSE.1989.559775
Usage of this product signifies your acceptance of the Terms of Use.