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Compaction with General Synchronous Timing
May 1988 (vol. 14 no. 5)
pp. 595-599

In current microcode generation systems, one simplification that is frequently made is to assume an absence of timing restrictions. It is critical that timing is considered when the target architecture involves branch delays, volatile registers, or microoperations requiring multiple microinstructions to complete. A general form for representing synchronous timing in clocked microarchitectures and methods of compacting data-dependency graphs with general timing are described.

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Index Terms:
compilers; general synchronous timing; microcode generation systems; target architecture; branch delays; volatile registers; microoperations; multiple microinstructions; clocked microarchitectures; data-dependency graphs; microprogramming; program compilers; synchronisation
V.H. Allen, R.A. Mueller, "Compaction with General Synchronous Timing," IEEE Transactions on Software Engineering, vol. 14, no. 5, pp. 595-599, May 1988, doi:10.1109/32.6137
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