Leandro Fiorin , Faculty of Lugano, Lugano
Mariagiovanna Sami , Politecnico di Milano, Milano
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TDSC.2013.28
As the complexity of designs increases and technology scales down into the deep-submicron domain, the probability of malfunctions and failures in the Networks-on-Chip (NoCs) components increases. In this work, we focus on the study and evaluation of techniques for increasing reliability and resilience of Network Interfaces (NIs) within NoC-based Multiprocessor System-on-Chip (MPSoC) architectures. NIs act as interfaces between IP cores and the communication infrastructure; the faulty behavior of one of them could affect therefore the overall system. In this work, we propose a functional fault model for the NI components by evaluating their susceptibility to faults. We present a two-level fault-tolerant solution that can be employed for mitigating the effects of both permanent and temporary faults in the NI. Experimental simulations show that with a limited overhead we can obtain an NI reliability comparable to the one obtainable by implementing the system by using standard Triple Modular Redundancy techniques, while saving up to 48% in area, as well as obtaining a significant energy reduction.
Nickel, Circuit faults, Table lookup, Routing, Registers, Fault tolerance, Fault tolerant systems, On-chip interconnection networks, Reliability, Testing, and Fault-Tolerance
Leandro Fiorin, Mariagiovanna Sami, "Fault-Tolerant Network Interfaces for Networks-on-Chip", IEEE Transactions on Dependable and Secure Computing, , no. 1, pp. 1, PrePrints PrePrints, doi:10.1109/TDSC.2013.28