CSDL Home IEEE Transactions on Dependable and Secure Computing 2011 vol.8 Issue No.05 - September/October

Subscribe

Issue No.05 - September/October (2011 vol.8)

pp: 756-769

Hong Luo , Tsinghua University, Beijing

Ku He , Tsinghua University, Beijing

Rong Luo , Tsinghua University, Beijing

Huazhong Yang , Tsinghua University, Beijing

Yuan Xie , Pennsylvania State University, University Park

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/TDSC.2010.41

ABSTRACT

As technology scales, Negative Bias Temperature Instability (NBTI), which causes temporal performance degradation in digital circuits by affecting PMOS threshold voltage, is emerging as one of the major circuit reliability concerns. In this paper, we first investigate the impact of NBTI on PMOS devices and propose a temporal performance degradation model that considers the temperature variation between active and standby mode. We then discuss the resemblance between NBTI and leakage mechanisms, and find out that the impact of input vector and internal node on leakage and NBTI is different; hence, leakage and NBTI should be optimized simultaneously. Based on this, we study the impact of standby leakage reduction techniques (including input vector control and sleep transistor insertion) on circuit performance degradation considering active and standby temperature differences. We demonstrate the potential mitigation of the circuit performance degradation by these techniques.

INDEX TERMS

Negative bias temperature instability (NBTI), leakage reduction, temperature-aware NBTI modeling, circuit performance degradation.

CITATION

Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie, "Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation",

*IEEE Transactions on Dependable and Secure Computing*, vol.8, no. 5, pp. 756-769, September/October 2011, doi:10.1109/TDSC.2010.41REFERENCES

- [1] V. Huard, M. Denais, and C. Parthasarathy, "NBTI Degradation: From Physical Mechanisms to Modelling,"
Microelectronics Reliability, vol. 46, no. 1, pp. 1-23, 2006.- [2] S. Nassif, K. Bernstein, D. Frank, A. Gattiker, W. Haensch, B. Ji, E. Nowak, D. Pearson, and N. Rohrer, "High Performance CMOS Variability in the 65nm Regime and Beyond"
Proc. Int'l Electron Devices Meeting (IEDM '07), pp. 569-571, Dec. 2007.- [3] J. Stathis and S. Zafar, "The Negative Bias Temperature Instability in MOS Devices: A Review,"
Microelectronics Reliability, vol. 46, nos. 2-4, pp. 270-286, 2006.- [4] G. Chen, M. Li, C. Ang, J. Zheng, and D. Kwong, "Dynamic NBTI of p-MOS Transistors and Its Impact on MOSFET Scaling,"
IEEE Electron Device Letters, vol. 23, no. 12, pp. 734-736, Dec. 2002.- [5] S. Mahapatra, P. Bharath Kumar, T. Dalei, D. Sana, and M. Alam, "Mechanism of Negative Bias Temperature Instability in CMOS Devices: Degradation, Recovery and Impact of Nitrogen,"
Proc. Technical Digital Int'l Electron Device Meeting, pp. 105-108, 2004.- [6] S.V. Kumar, C.H. Kim, and S.S. Sapatnekar, "An Analytical Model for Negative Bias Temperature Instability,"
Proc. IEEE/ACM Int'l Conf. Computer-Aided Design, 2006.- [7] K. Roy, S. Mukhopadhay, and H. Mahmoodi-Meimand, "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicro-Meter CMOS Circuits,"
Proc. IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.- [8] S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, and S. Vrudhula, "Predictive Modeling of the Nbti Effect for Reliable Design,"
Proc. Custom Integrated Circuits Conf. (CICC), 2006.- [9] L. Yuan and G. Qu, "A Combined Gate Replacement and Input Vector Control Approach for Leakage Current Reduction,"
IEEE Trans. Very Large Scale Integration Systems, vol. 14, no. 2, pp. 173-182, Feb. 2006.- [10] H. Rahman and C. Chakrabarti, "An Efficient Control Point Insertion Technique for Leakage Reduction of Scaled CMOS Circuits,"
IEEE Trans. Circuits and Systems II: Express Briefs, vol. 52, no. 8, pp. 496-500, Aug. 2005.- [11] A. Goetzberger and H. Nigh, "Surface Charge After Annealing of Al-SiO2-Si Structures under Bias,"
Proc. IEEE, vol. 54, no. 10, p. 1454, 1966.- [12] A. Goetzberger, A. Lopez, and R. Strain, "On the Formation of Surface States During Stress Aging of Thermal Si-SiO2 Interfaces,"
J. Electrochemical Soc., vol. 120, pp. 90-96, 1973.- [13] D.K. Schroder and J.A. Babcock, "Negative Bias Temperature Instability: Road to Cross in Deep Submicron Silicon Semiconductor Manufacturing,"
J. Applied Physics, vol. 94, no. 1, pp. 1-18, 2003.- [14] S. Mahapatra and M. Alam, "A Predictive Reliability Model for PMOS Bias Temperature Degradation,"
Proc. Technical Digital Int'l Electron Device Meeting, pp. 505-508, 2002.- [15] B. Zhu, J. Suehle, J. Bernstein, and Y. Chen, "Mechanism of Dynamic NBTI of pMOSFETs,"
Proc. IEEE Int'l Integrated Reliability Workshop Final Report, pp. 113-117, 2004.- [16] V. Huard and M. Denais, "Hole Trapping Effect on Methodology for DC and AC Negative Bias Temperature Instability Measurements in PMOS Transistors,"
Proc. Ann. IEEE Reliability Physics (Symp.), pp. 40-45, 2004.- [17] M. Alam, "A Critical Examination of the Mechanics of Dynamic NBTI for PMOSETs,"
Proc. Technical Digital Int'l Electron Device Meeting, pp. 14.4.1-14.4.4, 2003.- [18] S. Mahapatra, P. Kumar, and M. Alam, "Investigation and Modeling of Interface and Bulk Trap Generation During Negative Bias Temperature Instability of p-MOSFETs,"
IEEE Trans. Electron Devices, vol. 51, no. 9, pp. 1371-1379, Sept. 2004.- [19] B. Paul, K. Kang, H. Kufluoglu, M. Alam, and K. Roy, "Impact of NBTI on the Temporal Performance Degradation of Digital Circuits,"
IEEE Electron Device Letters, vol. 26, no. 8, pp. 560-562, Aug. 2005.- [20] R. Vattikonda, W. Wang, and Y. Cao, "Modeling and Minimization of PMOS NBTI Effect for Robust Nanometer Design,"
Proc. Design Automation Conf., pp. 1047-1052, 2006.- [21] S. Kumar, C. Kim, and S. Sapatnekar, "Impact of NBTI on SRAM Read Stability and Design for Reliability,"
Proc. Int'l Symp. Quality Electronic Design, pp. 210-218, 2006.- [22] B. Paul, K. Kang, H. Kufluoglu, M. Alam, and K. Roy, "Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits,"
Proc. Conf. Design, Automation and Test in Europe, vol. 1, pp. 1-6, 2006.- [23] J. Abella, X. Vera, and A. Gonzalez, "Penelope: The NBTI-Aware Processor,"
Proc. Ann. IEE/ACM Int'l Symp. (MICRO '07), pp. 85-96, Dec. 2007.- [24] L. Zhang, R.P. Dick, and L. Shang, "Scheduled Voltage Scaling for Increasing Lifetime in the Presence of NBTI,"
Proc. Asia and South Pacific Deisign Automation Conf. (ASP-DAC '09), pp. 492-497, 2009.- [25] S. Kumar, C. Kim, and S. Sapatnekar, "Adaptive Techniques for Overcoming Performance Degradation Due to Aging in Digital Circuits,"
Proc. Asia and South Pacific Deisign Automation Conf. (ASP-DAC '09), pp. 284-289, 2009.- [26] K. Kang, S. Gangwal, S. Park, and K. Roy, "NTBI Induced Performance Degradation in Logic and Memory Circuits: How Effectively Can We Approach a Reliability Solution?"
Proc. Asia and South Pacific Deisign Automation Conf. (ASP-DAC '08), pp. 726-731, Mar. 2008.- [27] S. Naffziger, B. Stackhouse, T. Grutkowski, D. Josephson, J. Desai, E. Alon, and M. Horowitz, "The Implementation of a 2-Core, Multi-Threaded Itanium Family Processor,"
IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 197-209, Jan. 2006.- [28] K. Skadron, M. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, "Temperature-Aware Microarchitecture,"
Proc. Int'l Symp. Computer Architecture (ISCA 2003), pp. 2-13, 2003.- [29] A. Agarwal, S. Mukhopadhyay, R.A.K. Roy, and C. Kim, "Leakage Power Analysis and Reduction for Nanoscale Circuits,"
IEEE MICRO, vol. 26, no. 2, pp. 68-80, Mar./Apr. 2006.- [30] Q. Wang and S. Vrudhula, "Algorithms for Minimizing Standby Power in Deep Submicrometer, Dual-Vt CMOS Circuits,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 3, pp. 306-318, Mar. 2002.- [31] A. Abdollahi, F. Fallah, and M. Pedram, "Leakage Current Reduction in CMOS VLSI Circuits by Input Vector Control,"
IEEE Trans. Very Large Scale Integration Systems, vol. 12, no. 2, pp. 140-154, Feb. 2004.- [32] F. Gao and J. Hayes, "Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction,"
Proc. IEEE/ACM Int'l Conf. Computer Aided Design, pp. 527-532, 2004.- [33] R. Rao, F. Liu, J. Burns, and R. Brown, "A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits,"
Proc. IEEE/ACM Int'l Conf. Computer Aided Design, pp. 689-692, 2003.- [34] M. Johnson, D. Somasekhar, and K. Roy, "Models and Algorithms for Bounds On Leakage in CMOS Circuits,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 6, pp. 714-725, June 1999.- [35] D. Lee, W. Kwong, D. Blaauw, and D. Sylvester, "Analysis and Minimization Techniques for Total Leakage Considering Gate Oxide Leakage,"
Proc. Design Automation Conf., pp. 175-180., 2003.- [36] S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-v Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage Cmos,"
IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 847-854, Aug. 1995.- [37] J. Kao, S. Narendra, and A. Chandrakasan, "MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns,"
Proc. Design Automation Conf., pp. 495-500, 1998.- [38] M. Anis, S. Areibi, and M. Elmasry, "Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique,"
Proc. Design Automation Conf., pp. 480-485, 2002.- [39] C. Long and L. He, "Distributed Sleep Transistor Network for Power Reduction,"
IEEE Trans. Very Large Scale Integration Systems, vol. 12, no. 9, pp. 937-946, Sept. 2004.- [40] B. Calhoun and F. Honor, A. Chandrakasan, "A Leakage Reduction Methodology for Distributed MTCMOS,"
IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 818-826, May 2004.- [41] V. Khandelwal and A. Srivastava, "Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors,"
Proc. Int'l Conf. Computer-Aided Design, pp. 533-536, 2004.- [42] Y. Wang, H. Lin, R. Luo, H. Yang, and H. Wang, "Simultaneous Fine-Grain Sleep Transistor Placement and Sizing for Leakage Optimization,"
Proc. Int'l Symp. Quality of Electronic Designs, pp. 723-728, 2006.- [43] Nanoscale Integration and Modeling (NIMO) Group, ASU. Predictive Technology Model (PTM), url=http:/www.eas. asu.edu~ptm/, 2007.
- [44] Y. Wang, H. Yang, and H. Wang, "Signal-Path Level Dual-Vt Assignment for Leakage Power Reduction,"
J. Circuits, System and Computers, vol. 15, no. 2, pp. 179-216, 2006.- [45] F. Kreith, Ed.,
The CRC Handbook of Thermal Engineering. CRC Press, 2000.- [46] S. Kevin, S. Mircea, R.H. Wei, V. Sivakumar, S. Karthik, and T. David, "Temperature-Aware Computer Systems: Opportunities and Challenges,"
IEEE Micro, vol. 23, no. 6, pp. 52-61, Nov./Dec. 2003.- [47] A.T. Krishnan, S. Chakravarthi, P. Nicollian, V. Reddy, and S. Krishnan, "Negative Bias Temperature Instability Mechanism: The Role of Molecular Hydrogen,"
Applied Physics Letters, vol. 88, no. 15, pp. 153-518, 2006.- [48] C. Liu, M. Lee, C.-Y. Lin, J. Chen, K. Schruefer, J. Brighten, N. Rovedo, T. Hook, M. Khare, S.-F. Huang, C. Wann, T.-C. Chen, and T. Ning, "Mechanism and Process Dependence of Negative Bias Temperature Instability (NBTI) for pMOSFETs with Ultrathin Gate Dielectrics,"
Proc. Int'l Electron Devices Meeting (IEDM), pp. 39.2.1-39.2.4, 2001.- [49] Y. Wang, X. Chen, W. Wang, V. Balakrishnan, Y. Cao, Y. Xie, and H. Yang, "On the Efficacy of Input Vector Control to Mitigate Nbti Effects and Leakage Power,"
Proc. Int'l Symp. Quality of Electronic Design (ISQED '09), pp. 19-26, Mar. 2009.- [50] T. Sakurai and A. Newton, "Alpha-Power Law Mosfet Model and Its Applications to CMOS Inverter Delay and Other Formulas,"
IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584-594, Apr. 1990.- [51] W. Wang, V. Reddy, B. Yang, V. Balakrishnan, S. Krishnan, and Y. Cao, "Statistical Prediction of Circuit Aging Under Process Variations,"
Proc. Custom Integrated Circuits Conf. (CICC '08), pp. 13-16, Sept. 2008. |