
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
Ilia Polian, John P. Hayes, Sudhakar M. Reddy, Bernd Becker, "Modeling and Mitigating Transient Errors in Logic Circuits," IEEE Transactions on Dependable and Secure Computing, vol. 8, no. 4, pp. 537547, July/August, 2011.  
BibTex  x  
@article{ 10.1109/TDSC.2010.26, author = {Ilia Polian and John P. Hayes and Sudhakar M. Reddy and Bernd Becker}, title = {Modeling and Mitigating Transient Errors in Logic Circuits}, journal ={IEEE Transactions on Dependable and Secure Computing}, volume = {8}, number = {4}, issn = {15455971}, year = {2011}, pages = {537547}, doi = {http://doi.ieeecomputersociety.org/10.1109/TDSC.2010.26}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Dependable and Secure Computing TI  Modeling and Mitigating Transient Errors in Logic Circuits IS  4 SN  15455971 SP537 EP547 EPD  537547 A1  Ilia Polian, A1  John P. Hayes, A1  Sudhakar M. Reddy, A1  Bernd Becker, PY  2011 KW  Soft errors KW  error tolerance KW  selective hardening KW  transient faults. VL  8 JA  IEEE Transactions on Dependable and Secure Computing ER   
[1] M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design. Computer Science Press, 1990.
[2] S. Almukhaizim, T. Verdel, and Y. Makris, “CostEffective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case,” Proc. IEEE Int'l Conf. Computer Design, pp. 194197, 2003.
[3] H. Ando, R. Kan, Y. Tosaka, K. Takahisa, and K. Hatanaka, “Validation of Hardware Error Recovery Mechanisms for the SPARC64 V Microprocessor,” Proc. Int'l Conf. Dependable Systems and Networks, pp. 6269, 2008.
[4] H. Asadi and M. Tahoori, “Soft Error Modeling and Protection for Sequential Elements,” Proc. IEEE Defect and Fault Tolerance Symp., pp. 463471, 2005.
[5] M. Breuer and H. Zhu, “An Illustrated Methodology for Analysis of Error Tolerance,” IEEE Design and Test of Computers, vol. 25, no. 2, pp. 168177, Mar./Apr. 2008.
[6] M.A. Breuer, “Testing for Intermittent Faults in Digital Circuits,” IEEE Trans. Computers, vol. 22, no. 3, pp. 241246, Mar. 1973.
[7] P.E. Dodd and L.W. Massengill, “Basic Mechanisms and Modeling of SingleEvent Upset in Digital Microelectronics,” IEEE Trans. Nuclear Science, vol. 50, no. 3, pp. 583602, June 2003.
[8] K. Driscoll, B. Hall, H. Sivencrona, and P. Zumsteg, “Byzantine Fault Tolerance, from Theory to Reality,” Proc. Int'l Conf. Computer Safety, Reliability and Security, pp. 235248, 2003.
[9] E.N. Elnozahy, L. Alvisi, Y.M. Wang, and D.B. Johnson, “A Survey of RollbackRecovery Protocols in MessagePassing Systems,” ACM Computing Surveys, vol. 34, no. 3, pp. 375408, 2002.
[10] R. Garg, N. Jayakumar, S.P. Khatri, and G. Choi, “A Design Approach for RadiationHard Digital Electronics,” Proc. IEEE Design Automation Conf., pp. 773778, 2006.
[11] J.P. Hayes, I. Polian, and B. Becker, “An Analysis Framework for TransientError Tolerance,” Proc. Very LargeScale Integration Test Symp., pp. 249255, 2007.
[12] S. Hellebrand, C.G. Zoellin, H.J. Wunderlich, S. Ludwig, T. Coym, and B. Straube, “A Refined Electrical Model for Particle Strikes and Its Impact on SEU Prediction,” Proc. IEEE Defect and Fault Tolerance Symp., 2007.
[13] E. Hill, M. Lipasti, and K. Saluja, “An Accurate FlipFlop Selection Technique for Reducing Logic SER,” Proc. Int'l Conf. Dependable Systems and Networks, pp. 3241, 2008.
[14] S.K. Jain and V.D. Agrawal, “Statistical Fault Analysis,” IEEE Design and Test of Computers, vol. 2, no. 1, pp. 3844, Jan./Feb. 1985.
[15] Z. Jiang and S. Gupta, “Threshold Testing: Improving Yield for Nanoscale VLSI,” IEEE Trans. ComputerAided Design of Integrated Circuits and Systems, vol. 28, no. 12, pp. 19931895, Dec. 2009.
[16] V. Joshi, R.R. Rao, D. Blaauw, and D. Sylvester, “Logic SER Reduction through Flip Flop Redesign,” Proc. Int'l Symp. Quality Electronic Design, pp. 611616, 2006.
[17] S. Krishnaswamy, G.F. Viamontes, I.L. Markov, and J.P. Hayes, “Probabilistic Transfer Matrices in Symbolic Reliability Analysis of Logic Circuits,” ACM Trans. Design Automation of Electronic Systems, vol. 13, no. 1, 2008.
[18] W.Y. Kung, C.S. Kim, and C.C.J. Kuo, “Spatial and Temporal Error Concealment Techniques for Video Transmission over Noisy Channels,” IEEE Trans. Circuits and Systems for Video Technology, vol. 16, no. 7, pp. 789802, July 2006.
[19] X. Li and D. Yeung, “ApplicationLevel Correctness and Its Impact on Fault Tolerance,” Proc. Int'l Symp. High Performance Computer Architecture, pp. 181192, 2007.
[20] J.W.S. Liu, W.K. Shin, K.J. Lin, R. Bettati, and J.Y. Chung, “Imprecise Computations,” Proc. IEEE, vol. 82, no. 1, pp. 8394, Jan. 1994.
[21] M. May, M. Alles, and N. Wehn, “A Case Study in ReliabilityAware Design: A Resilient LDPC Code Decoder,” Proc. Conf. Design, Automation and Test in Europe, 2008.
[22] K. Mohanram and N.A. Touba, “CostEffective Approach for Reducing Soft Error Failure Rate in Logic Circuits,” Proc. IEEE Int'l Test Conf., pp. 893901, 2003.
[23] H.T. Nguyen and Y. Yagil, “A Systematic Approach to SER Estimation and Solutions,” Proc. Int'l Reliability Physics Symp., pp. 6070, 2003.
[24] M. Nicolaidis, “GRAAL: A FaultTolerant Architecture for Enabling Nanometric Technologies,” Proc. Int'l OnLine Test Symp., p. 255, 2007.
[25] A.K. Nieuwland, S. Jasarevic, and G. Jerin, “Combinational Logic Soft Error Analysis and Protection,” Proc. Int'l OnLine Test Symp., 2006.
[26] D. Nowroth, I. Polian, and B. Becker, “A Study of Cognitive Resilience in a JPEG Compressor,” Proc. Int'l Conf. Dependable Systems and Networks, pp. 3241, 2008.
[27] Z. Pan and M.A. Breuer, “Basing Acceptable ErrorTolerant Performance on SignificanceBased ErrorRate (SBER),” Proc. Very LargeScale Integration. Test Symp., 2008.
[28] I. Polian, B. Becker, M. Nakasato, S. Ohtake, and H. Fujiwara, “LowCost Hardening of Image Processing Applications against Soft Errors,” Proc. Int'l Symp. Defect and Fault Tolerance, pp. 274279, 2006.
[29] I. Polian, J.P. Hayes, S. Kundu, and B. Becker, “Transient Fault Characterization in Dynamic Noisy Environments,” Proc. IEEE Int'l Test Conf., pp. 10391048, 2005.
[30] I. Polian, S.M. Reddy, and B. Becker, “Scalable Calculation of Logical Masking Effects for Selective Hardening against Soft Errors,” Proc. IEEE Int'l Symp. Very LargeScale Integration, pp. 257262, 2008.
[31] C. Rusu, A. Bougerol, L. Anghel, C. Weulerse, N. Buard, S. Benhammadi, N. Renaud, G. Hubert, F. Wrobel, T. Carriere, and R. Gaillard, “Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells,” Proc. Int'l OnLine Test Symp., pp. 137145, 2007.
[32] J. Savir, “Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection,” IEEE Trans. Computers, vol. 29, no. 5, pp. 410416, May 1980.
[33] S.A. Seshia, W. Li, and S. Mitra, “VerificationGuided Soft Error Resilience,” Proc. Conf. Design, Automation and Test in Europe, 2007.
[34] S. Shahidi and S.K. Gupta, “ERTG: A Test Generator for ErrorRate Testing,” Proc. IEEE Int'l Test Conf., 2007.
[35] P. Shivakumar, M. Kistler, W. Keckler, D. Burger, and L. Alvisi, “Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic,” Proc. Int'l Conf. Dependable Systems and Networks, pp. 389398, 2002.
[36] F. Wang and V. Agrawal, “Soft Error Rate Determination for Nanometer CMOS VLSI logic,” Proc. Southeastern Symp. System Theory, pp. 324328, 2008.
[37] H.J. Wunderlich, “PROTEST: A Tool for Probabilistic Testability Analysis,” Proc. IEEE Design Automation Conf., 1985.
[38] M. Zhang, S. Mitra, T.M. Mak, N. Seifert, N.J. Wang, Q. Shi, K.S. Kim, N.R. Shanbhag, and S.J. Patel, “Sequential Element Design with BuiltIn Soft Error Resilience,” IEEE Trans. Very LargeScale Integration Systems, vol. 14, no. 12, pp. 13681378, Dec. 2006.
[39] M. Zhang and N.R. Shanbhag, “Soft ErrorRate Analysis (SERA) Methodology,” IEEE Trans. ComputerAided Design, vol. 25, no. 10, pp. 21402155, Oct. 2006.
[40] C.G. Zoellin, H.J. Wunderlich, I. Polian, and B. Becker, “Selective Hardening in Early Design Steps,” Proc. European Test Symp., pp. 185190, 2008.